Add &mask syntax

This change adds a new syntax for bitfield definitions:

field: &0xff00 top 16-bits

This allows a mask (rather than mask << shift) value to be specified.

Signed-off-by: Jeremy Kerr <jk@ozlabs.org>

diff --git a/ChangeLog b/ChangeLog
index 0d9feae647ba492da70e88fe89a475a9d9d1e425..094262f37d4d2ae22ab85040230dcfca85312835 100644 (file)
--- a/ChangeLog
+++ b/ChangeLog
@@ -1,4 +1,5 @@
 version ??
+       * Add support for &mask syntax
        * Allow alternate (bit 0 is lsb) bit numbering scheme
        * Add support for mask<<shift field definitions
        * Add configuration for a few radeon registers

diff --git a/bitfield b/bitfield
index 467bf6ba7e6d50da91df2a16dabb886393f9798b..3851c4c9119bb1ecdecf0c47c1057df780cad626 100644 (file)
--- a/bitfield
+++ b/bitfield
@@ -57,6 +57,10 @@ class bitfield:
                                bits.insert(0, width - i - 1 - shift)
                return bits
 
+       @staticmethod
+       def mask_to_bits(width, mask):
+               return bitfield.mask_and_shift_to_bits(width, mask, 0)
+
        @staticmethod
        def parse_bitfield(line, reg):
                a = line.split(None, 1)
@@ -78,6 +82,10 @@ class bitfield:
                                        s.split('<<'))
                                bits.extend(bitfield.mask_and_shift_to_bits( \
                                        reg.width, mask, shift))
+                       elif s.startswith('&'):
+                               mask = int(s[1:], 0)
+                               bits.extend(bitfield.mask_to_bits(reg.width, \
+                                                       mask))
                        else:
                                bits.append(reg.bit_number(int(s)))