References to the variable called CC in makefiles need to be
written as $(CC) not $CC. Make interprets the latter as a reference
to the (nonexistent) variable C followed by a literal C.
Fixes: 4e713175 ("make: Avoid using host include for cross-compiling")
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
#LIBS += -lshadow $(LIBS)
endif
#LIBS += -lshadow $(LIBS)
endif
-ifneq ($(wildcard $(shell $CC --print-sysroot)/usr/include/crypt.h),)
+ifneq ($(wildcard $(shell $(CC) --print-sysroot)/usr/include/crypt.h),)
CFLAGS += -DHAVE_CRYPT_H=1
LIBS += -lcrypt
endif
CFLAGS += -DHAVE_CRYPT_H=1
LIBS += -lcrypt
endif
ifdef NEEDDES
ifndef USE_CRYPT
ifdef NEEDDES
ifndef USE_CRYPT
-CFLAGS += -I$(shell $CC --print-sysroot)/usr/include/openssl
+CFLAGS += -I$(shell $(CC) --print-sysroot)/usr/include/openssl
LIBS += -lcrypto
else
CFLAGS += -DUSE_CRYPT=1
LIBS += -lcrypto
else
CFLAGS += -DUSE_CRYPT=1