5 * Expected configuration on the master is SPI mode 0
7 * - SCK idle state is 0
8 * - We latch input on positive edges of SCK
9 * - We setup output on negative edge of SCK
11 * IE. For a PIC, this means setting:
17 input reset, /* Async system reset */
22 input [7:0] wdata, /* Output data */
23 output reg [7:0] rdata, /* Input data */
24 output rx, /* One-sysclk signal of a new byte */
25 output reg cmd /* Indicate first byte of rx, variable len */
39 always@(posedge sck or posedge _scs) begin
47 /* Shift input, latch on positive edge of sck. We only shift in 7
48 * bits as we'll take sdi directly into the final latch.
50 always@(posedge sck) begin
52 in_sr[6:0] <= { in_sr[5:0], sdi };
56 /* We latch the input byte so it remains stable for a while byte for
57 * consumption by sysclk domain.
59 always@(posedge sck) begin
60 if (!_scs && cnt == 3'b111) begin
61 rdata[7:0] <= { in_sr[6:0], sdi };
65 /* Shift output. We latch "data" on bit 7 falling edge (so before we
66 * set new_byte and thus before rx catches up sysclk domain).
68 * That means we are ahead by one bit, so we add a one bit delay latch
72 always@(negedge sck or posedge _scs) begin
76 if (cnt == 3'b111) begin
79 out_sr[7:0] <= { out_sr[6:0], 1'b0 };
84 always@(negedge sck or posedge _scs) begin
92 /* We keep output hi-z if chip select not set. We do have a transcient
93 * undefined state between _scs assertion and the first clock, which
94 * I'm happy to ignore for now
96 assign sdo = _scs ? 1'bz : tx;
98 /* Now we need to generate rx. It's tricky because sck can/will stop
99 * immediately after the last bit.
101 * What we do is we generate a signal "new_byte" at the same time as
102 * latching the input byte, which we clear half way through the next
103 * byte. We then double flip-flop synchronize that into sysclk domain
104 * where we do an edge detection. If we lose sck, this signal will
105 * remains set until we start a new transmission, but since the delay
106 * between two transmissions is unpredictable, we must make sure we
107 * don't clear it until half way through the new byte (ie, we keep it
108 * set even when SCS is gone). For the same reason we don't
109 * clear our input latch either when SCS is gone.
111 * Now, the nasty thing is we need to reset that dude asynchronously
112 * from sysclk domain, which could probably use some sychronisation
113 * too. For now, we assume the sysclk reset happens long enough before
114 * sck toggles. This will do for us, but in a more complex system,
115 * some logic might be needed to ensure sck is effectively masked
116 * out until a few clocks after reset completes to avoid metastability
118 * Note: FPGAs are nice, we could probably just rely on new_byte being
119 * 0 at powerup time :-)
121 always@(posedge sck or posedge reset) begin
125 if (cnt == 3'b111) begin
127 end else if (cnt == 3'b011) begin
133 always@(posedge sysclk or posedge reset) begin
145 assign rx = rx2 & !rx3;
147 /* "first" is set in sck domain during clocking of first byte,
148 * and flushed into "cmd" at bit 7, thus cmd moves along with
149 * the data itself and will be sampled with the data by the user.
151 always@(posedge sck or posedge _scs) begin
154 end else if (cnt == 3'b111) begin