fpga/sim_pic.v

   1 `timescale 1ns / 100ps
   2
   3 `define ROM_MAX 'h20000
   4
   5 `define BB_WRITE                8'h80
   6 `define BB_AUTOINC              8'h40
   7
   8 `define BB_REG_CTRL_BASE        6'h00
   9 `define BB_REG_CPU_BASE         6'h10
  10 `define BB_REG_MEM_BASE         6'h20
  11 `define BB_REG_IWM_BASE         6'h28
  12 `define BB_REG_SCSI_BASE        6'h30
  13 `define BB_REG_SCOPE_BASE       6'h38
  14
  15 /* SCSI Backbus interface */
  16 `define BB_REG_LINES    0
  17 `define BB_LINES_BSY    7
  18 `define BB_LINES_SEL    6
  19 `define BB_LINES_ACK    5
  20 `define BB_LINES_ATN    4
  21 `define BB_LINES_RST    3
  22
  23 `define BB_REG_ASSERT   1
  24 `define BB_ASSERT_BSY   7
  25 `define BB_ASSERT_SEL   6
  26 `define BB_ASSERT_CD    5
  27 `define BB_ASSERT_IO    4
  28 `define BB_ASSERT_MSG   3
  29 `define BB_ASSERT_REQ   2
  30 `define BB_ASSERT_RST   1
  31 `define BB_ASSERT_AUTO  0       /* Automatic mode */
  32
  33 `define BB_REG_ODATA    2
  34 `define BB_REG_IDATA    3
  35 `define BB_REG_ACNT_HI  4
  36 `define BB_REG_ACNT_LO  5
  37
  38 module sim_pic
  39 (
  40         input                   sdi,
  41         output reg              sdo,
  42         output reg              sck,
  43         output reg              _spi_cs,
  44         input                   scsi_hshake,
  45         output reg              nmi);
  46         integer rom_file;
  47         integer rom_size;
  48         reg [7:0] rom[0:`ROM_MAX];
  49         reg [7:0] scsi_asserts;
  50         reg [7:0] scsi_cdb[0:11];
  51         reg [7:0] scsi_buf[0:2047];
  52         integer   dbg_foo;
  53
  54         /* SPI half clock period */
  55         parameter SPI_HCLOCK    = 40;
  56         /* Setup time of data vs rising clock edge */
  57         parameter SPI_HEAD      = 4;
  58
  59         task do_spi;
  60                 input [7:0] out_byte;           /* Out to FPGA */
  61                 output reg [7:0] in_byte;       /* In from FPGA */
  62                 reg [7:0]    in_sr;
  63                 reg [7:0]    out_sr;
  64                 begin
  65                         in_sr = 8'hff;
  66                         out_sr = out_byte;
  67                         repeat(8) begin
  68                                 sck = 0;
  69                                 #(SPI_HCLOCK-SPI_HEAD);
  70                                 sdo = out_sr[7];
  71                                 out_sr = { out_sr[6:0], 1'b0 };
  72                                 in_sr = { in_sr[6:0], sdi };
  73                                 #SPI_HEAD sck = 1;
  74                                 #SPI_HCLOCK;
  75                         end
  76                         sck =  0;
  77                         in_byte = in_sr;
  78                 end
  79         endtask // do_spi
  80
  81         task run_to;
  82                 input [23:0] addr;
  83                 reg [7:0]    stat;
  84                 begin
  85                         /* Set breakpoint */
  86                         _spi_cs = 0;
  87                         do_spi(`BB_WRITE | `BB_AUTOINC | `BB_REG_CPU_BASE | 8, val);
  88                         do_spi(addr[23:16], val);
  89                         do_spi(addr[15:8], val);
  90                         do_spi(addr[7:0], val);
  91                         _spi_cs = 1;
  92                         #(SPI_HCLOCK*4);
  93
  94                         /* Run CPU interface */
  95                         _spi_cs = 0;
  96                         do_spi(`BB_WRITE | `BB_REG_CPU_BASE | 6, val);
  97                         do_spi(8'h42, val); /* RUN + BKEN */
  98                         _spi_cs = 1;
  99                         #(SPI_HCLOCK*4);
 100
 101                         stat = 0;
 102                         while(!stat[3]) begin
 103                                 /* Get CPU status */
 104                                 _spi_cs = 0;
 105                                 do_spi(`BB_REG_CPU_BASE | 7, val);
 106                                 do_spi(8'hff, val);
 107                                 do_spi(8'hff, stat);
 108                                 _spi_cs = 1;
 109 //                              $display("stat: %h", stat);
 110 //                              #(SPI_HCLOCK*40);
 111                         end
 112                 end
 113         endtask // run_to
 114
 115         task scsi_set_lines;
 116                 input [7:0] lines;
 117                 begin
 118                         _spi_cs = 0;
 119                         do_spi(`BB_WRITE | `BB_REG_SCSI_BASE | `BB_REG_ASSERT, val);
 120                         do_spi(lines, val);
 121                         _spi_cs = 1;
 122                         #(SPI_HCLOCK*4);
 123                 end
 124         endtask
 125
 126         task scsi_set;
 127                 input integer line;
 128                 begin
 129                         scsi_asserts[line] = 1'b1;
 130                         scsi_set_lines(scsi_asserts);
 131                 end
 132         endtask
 133
 134         task scsi_clear;
 135                 input integer line;
 136                 begin
 137                         scsi_asserts[line] = 1'b0;
 138                         scsi_set_lines(scsi_asserts);
 139                 end
 140         endtask
 141
 142         task scsi_set_autocnt;
 143                 input integer cnt;
 144                 begin
 145                         _spi_cs = 0;
 146                         do_spi(`BB_WRITE | `BB_AUTOINC |
 147                                `BB_REG_SCSI_BASE | `BB_REG_ACNT_HI, val);
 148                         do_spi(cnt[15:8], val);
 149                         do_spi(cnt[7:0], val);
 150                         _spi_cs = 1;
 151                         #(SPI_HCLOCK*4);
 152                 end
 153         endtask
 154
 155         task scsi_set_data;
 156                 input [7:0] data;
 157                 begin
 158                         _spi_cs = 0;
 159                         do_spi(`BB_WRITE | `BB_REG_SCSI_BASE | `BB_REG_IDATA, val);
 160                         do_spi(data, val);
 161                         _spi_cs = 1;
 162                         #(SPI_HCLOCK*4);
 163                 end
 164         endtask
 165
 166         task scsi_get_data;
 167                 output [7:0] val;
 168                 reg [7:0]    dummy;
 169                 begin
 170                         _spi_cs = 0;
 171                         do_spi(`BB_REG_SCSI_BASE | `BB_REG_ODATA, dummy);
 172                         do_spi(8'hff, dummy);
 173                         do_spi(8'hff, val);
 174                         _spi_cs = 1;
 175                         #(SPI_HCLOCK*4);
 176                 end
 177         endtask
 178
 179         task scsi_get_lines;
 180                 output [7:0] val;
 181                 reg [7:0]    dummy;
 182                 begin
 183                         _spi_cs = 0;
 184                         do_spi(`BB_REG_SCSI_BASE | `BB_REG_LINES, dummy);
 185                         do_spi(8'hff, dummy);
 186                         do_spi(8'hff, val);
 187                         _spi_cs = 1;
 188                         #(SPI_HCLOCK*4);
 189                 end
 190         endtask
 191
 192         task scsi_do_cmd;
 193                 output integer len;
 194                 output [7:0]   stat;
 195                 output         direction;
 196                 integer        i;
 197
 198                 begin
 199                         stat = 0;
 200                         len = 0;
 201                         direction = 0;
 202                         case(scsi_cdb[0])
 203                                 'h12: begin /* INQUIRY */
 204                                         direction = 1;
 205                                         for (i=0; i < 256; i = i + 1)
 206                                           scsi_buf[i] = 0;
 207                                         scsi_buf[4] = 32;
 208                                         scsi_buf[8] = 'h46;
 209                                         scsi_buf[9] = 'h4f;
 210                                         scsi_buf[10] = 'h4f;
 211                                         scsi_buf[16] = 'h42;
 212                                         scsi_buf[17] = 'h41;
 213                                         scsi_buf[18] = 'h52;
 214                                         len = scsi_cdb[4];
 215                                         $display("CMD: INQUIRY 0x%h bytes", len);
 216                                 end
 217                                 'h08: begin /* READ6 */
 218                                         direction = 1;
 219                                         len = 512 * scsi_cdb[4];
 220                                         if (len == 0)
 221                                           len = 512 * 256;
 222                                         $display("CMD: READ6 0x%h bytes", len);
 223                                 end
 224                                 'h0a: begin /* WRITE6 */
 225                                         direction = 0;
 226                                         len = 512 * scsi_cdb[4];
 227                                         if (len == 0)
 228                                           len = 512 * 256;
 229                                         $display("CMD: WRITE6 0x%h bytes", len);
 230                                 end
 231                                 'h28: begin /* READ10 */
 232                                         direction = 1;
 233                                         len = 512 * (scsi_cdb[7] * 256 + scsi_cdb[8]);
 234                                         $display("CMD: READ10 0x%h bytes", len);
 235                                 end
 236                                 'h2a: begin /* WRITE10 */
 237                                         direction = 0;
 238                                         len = 512 * (scsi_cdb[7] * 256 + scsi_cdb[8]);
 239                                         $display("CMD: WRITE10 0x%h bytes", len);
 240                                 end
 241                                 default: begin
 242                                         stat = 1; /* CHECK CONDITION */
 243                                 end
 244                         endcase
 245                 end
 246         endtask // scsi_init_cmd
 247
 248         task do_scsi;
 249                 reg [7:0] lines;
 250                 reg [7:0] data;
 251                 integer   len, llen;
 252                 reg [7:0] stat;
 253                 reg       direction;
 254
 255                 begin
 256                         scsi_get_lines(lines);
 257                         $display("Waiting selection... Lines: %h", lines);
 258                         while (!lines[`BB_LINES_SEL] || lines[`BB_LINES_BSY])
 259                           scsi_get_lines(lines);
 260                         scsi_get_data(data);
 261                         $display("Select ID: %h lines %h", data, lines);
 262                         stat = 0;
 263                         if (!data[6])
 264                           $display("Wrong ID !");
 265                         else begin
 266                                 $display("Setting BSY");
 267                                 scsi_set(`BB_ASSERT_BSY);
 268                                 $display("Waiting !SEL...");
 269                                 while(lines[`BB_LINES_SEL])
 270                                   scsi_get_lines(lines);
 271                                 $display("Setting CMD, starting cmd transfer");
 272                                 scsi_set(`BB_ASSERT_CD);
 273                                 len = 1;
 274                                 i = 0;
 275                                 stat = 0;
 276                                 while(len) begin
 277                                         scsi_set(`BB_ASSERT_REQ);
 278                                         while(!lines[`BB_LINES_ACK])
 279                                           scsi_get_lines(lines);
 280                                         scsi_get_data(data);
 281                                         $display("CMD %h = %h", i, data);
 282                                         scsi_cdb[i] = data;
 283                                         len = len - 1;
 284                                         i = i + 1;
 285                                         if (i == 1) begin
 286                                                 /* get command size */
 287                                                 case (data)
 288                                                         'h12: len =  6 - 1;
 289                                                         'h08: len =  6 - 1;
 290                                                         'h0a: len =  6 - 1;
 291                                                         'h28: len = 10 - 1;
 292                                                         'h2a: len = 10 - 1;
 293                                                         default: begin
 294                                                                 len = 0;
 295                                                                 stat = 1;
 296                                                         end
 297                                                 endcase
 298                                                 $display("CMD size adjust %h", len);
 299                                         end
 300                                         scsi_clear(`BB_ASSERT_REQ);
 301                                         while(lines[`BB_LINES_ACK])
 302                                           scsi_get_lines(lines);
 303                                 end
 304
 305                                 scsi_do_cmd(len, stat, direction);
 306                                 scsi_clear(`BB_ASSERT_CD);
 307                                 if (direction)
 308                                   scsi_set(`BB_ASSERT_IO);
 309                                 i = 0;
 310                                 while (len) begin
 311                                         scsi_set(`BB_ASSERT_AUTO);
 312                                         /* Break up transfer */
 313                                         if (len > 256)
 314                                           llen = 256;
 315                                         else
 316                                           llen = len;
 317                                         len = len - llen;
 318                                         $display("Chunk of %h, remaining %h...", llen, len);
 319                                         scsi_set_autocnt(llen);
 320                                         _spi_cs = 0;
 321                                         if (direction) begin
 322                                                 do_spi(`BB_WRITE | `BB_REG_SCSI_BASE | `BB_REG_IDATA, val);
 323                                                 while(llen != 0) begin
 324                                                         $display("Writing byte %h", i);
 325                                                         do_spi(scsi_buf[i], val);
 326                                                         wait (!scsi_hshake);
 327                                                         wait (scsi_hshake);
 328                                                         llen = llen - 1;
 329                                                         i = i + 1;
 330
 331                                                 end
 332                                         end else begin
 333                                                 do_spi(`BB_REG_SCSI_BASE | `BB_REG_ODATA, val);
 334                                                 #160;
 335                                                 wait (scsi_hshake);
 336                                                 do_spi(8'hff, val);
 337                                                 wait (!scsi_hshake);
 338                                                 $display("dummy1: %h", val);
 339                                                 wait (scsi_hshake);
 340                                                 do_spi(8'hff, val);
 341                                                 wait (!scsi_hshake);
 342                                                 $display("dummy2: %h", val);
 343                                                 wait (scsi_hshake);
 344                                                 do_spi(8'hff, val);
 345                                                 wait (!scsi_hshake);
 346                                                 $display("dummy3: %h", val);
 347                                                 while(llen != 0) begin
 348                                                         wait (scsi_hshake) ;
 349                                                         do_spi(8'hff, data);
 350                                                         if (llen > 3)
 351                                                           wait (!scsi_hshake);
 352                                                         scsi_buf[i] = data;
 353                                                         $display("DATA %h: %h", i, data);
 354                                                         llen = llen - 1;
 355                                                         i = i + 1;
 356                                                 end
 357                                         end
 358                                         _spi_cs = 1;
 359                                         #(SPI_HCLOCK*4);
 360                                         scsi_clear(`BB_ASSERT_AUTO);
 361                                 end
 362                                 $display("sending status %h", stat);
 363                                 scsi_set(`BB_ASSERT_CD);
 364                                 scsi_set(`BB_ASSERT_IO);
 365                                 scsi_set_data(stat);
 366                                 scsi_set(`BB_ASSERT_REQ);
 367                                 while(!lines[`BB_LINES_ACK])
 368                                   scsi_get_lines(lines);
 369                                 scsi_clear(`BB_ASSERT_REQ);
 370                                 while(lines[`BB_LINES_ACK])
 371                                   scsi_get_lines(lines);
 372                                 scsi_set(`BB_ASSERT_MSG);
 373                                 $display("Sending message");
 374                                 scsi_set_data(0);
 375                                 scsi_set(`BB_ASSERT_REQ);
 376                                 while(!lines[`BB_LINES_ACK])
 377                                   scsi_get_lines(lines);
 378                                 scsi_clear(`BB_ASSERT_REQ);
 379                                 while(lines[`BB_LINES_ACK])
 380                                   scsi_get_lines(lines);
 381                                 $display("Clearing phase & BSY");
 382                                 scsi_clear(`BB_ASSERT_CD);
 383                                 scsi_clear(`BB_ASSERT_IO);
 384                                 scsi_clear(`BB_ASSERT_MSG);
 385                                 scsi_clear(`BB_ASSERT_BSY);
 386                         end // else: !if(!data[6])
 387                 end
 388         endtask // do_scsi
 389
 390         task run_scsi;
 391                 begin
 392                         while(1) begin
 393                                 wait (scsi_hshake)
 394                                   do_scsi();
 395                         end
 396                 end
 397         endtask // run_scsi
 398
 399         task dump_latches;
 400                 reg [7:0] sval[0:7];
 401                 begin
 402                         /* Read latches */
 403                         _spi_cs = 0;
 404                         do_spi(`BB_AUTOINC | `BB_REG_CPU_BASE, val);
 405                         do_spi(8'hff, val);
 406                         do_spi(8'hff, sval[0]);
 407                         do_spi(8'hff, sval[1]);
 408                         do_spi(8'hff, sval[2]);
 409                         do_spi(8'hff, sval[3]);
 410                         do_spi(8'hff, sval[4]);
 411                         do_spi(8'hff, sval[5]);
 412                         _spi_cs = 1;
 413                         #(SPI_HCLOCK*4);
 414                         $display("RW:%b U:%b L:%b ADDR: %h DATA: %h",
 415                                  sval[5][0], sval[5][1], sval[5][2],
 416                                  { sval[0], sval[1], sval[2] },
 417                                  { sval[3], sval[4] });
 418                 end
 419         endtask // dump_latches
 420
 421         task step;
 422                 input integer count;
 423                 begin
 424                         repeat(count) begin
 425                                 /* Step CPU interface */
 426                                 _spi_cs = 0;
 427                                 do_spi(`BB_WRITE | `BB_REG_CPU_BASE | 6, val);
 428                                 do_spi(8'h82, val); /* RUN + STEP */
 429                                 _spi_cs = 1;
 430                                 #(SPI_HCLOCK*4);
 431
 432                                 /* Should wait for completion... not useful
 433                                  * in practice as SPI is too slow
 434                                  */
 435                         end // repeat (count)
 436                 end
 437         endtask // step
 438
 439
 440         reg [7:0] val;
 441 //      reg [7:0] scopedump[0:(2048 * 8)-1];
 442         integer   i;
 443
 444         initial begin
 445                 nmi = 0;
 446                 _spi_cs = 1;
 447                 sdo = 1'bz;
 448                 sck = 0;
 449                 scsi_asserts = 0;
 450
 451                 #100 _spi_cs = 0;
 452                 do_spi(`BB_AUTOINC | `BB_REG_CTRL_BASE, val);
 453                 do_spi(8'hff, val);
 454                 do_spi(8'hff, val);
 455                 $display("FPGA ID      = 0x%h", val);
 456                 do_spi(8'hff, val);
 457                 $display("FPGA Version = 0x%h", val);
 458                 do_spi(8'hff, val);
 459                 $display("FPGA Control = 0x%h", val);
 460                 _spi_cs = 1;
 461                 #(SPI_HCLOCK*4);
 462
 463                 /* Un-reset CPU */
 464                 _spi_cs = 0;
 465                 do_spi(`BB_WRITE | `BB_REG_CTRL_BASE | 2, val);
 466                 do_spi(8'h01, val);
 467                 _spi_cs = 1;
 468                 #(SPI_HCLOCK*4);
 469
 470 `ifdef foo
 471                 $display("Running to puts...");
 472                 run_to('h40326c);
 473                 dump_latches();
 474                 repeat(1000) begin
 475                         step(1);
 476                         dump_latches();
 477                 end
 478 `endif
 479
 480                 $display("Run....");
 481                 /* Run CPU interface */
 482                 _spi_cs = 0;
 483                 do_spi(`BB_WRITE | `BB_REG_CPU_BASE | 6, val);
 484                 do_spi(8'h02, val); /* RUN */
 485                 _spi_cs = 1;
 486                 #(SPI_HCLOCK*4);
 487                 run_scsi();
 488 `ifdef foo
 489                 $display("Running to iwm_test1...");
 490                 run_to('h4010f0);
 491                 dump_latches();
 492                 repeat(100) begin
 493                         step(1);
 494                         dump_latches();
 495                 end
 496 `endif
 497
 498 `ifdef foo
 499                 $display("Running to P_mBootBeep...");
 500                 run_to('h40028a);
 501                 dump_latches();
 502                 step(1);
 503                 dump_latches();
 504                 $display("Running to IWM init...");
 505                 run_to('h4000fc);
 506                 dump_latches();
 507                 step(1);
 508                 dump_latches();
 509                 $display("Running to P_ChecksumRomAndTestMemory...");
 510                 run_to('h400d76);
 511                 dump_latches();
 512                 step(1);
 513                 dump_latches();
 514                 $display("Running to P_BootPart2 (fake hit)...");
 515                 run_to('h400352);
 516                 dump_latches();
 517                 step(1);
 518                 dump_latches();
 519                 $display("Running to P_BootPart2...");
 520                 run_to('h400352);
 521                 dump_latches();
 522                 step(1);
 523                 dump_latches();
 524
 525                 repeat(1000) begin
 526                         step(1);
 527                         dump_latches();
 528                 end
 529 `endif
 530
 531 `ifdef __disabled__
 532                 /* Write memory from 0x201000 using mem SPI (ROM) */
 533                 $display("Loading ROM...");
 534                 rom_file = $fopenr("rom.bin");
 535                 rom_size = $fread(rom, rom_file, 0);
 536                 $fclose(rom_file);
 537                 _spi_cs = 0;
 538                 do_spi(`BB_WRITE | `BB_AUTOINC | `BB_REG_MEM_BSAE, val);
 539                 do_spi(8'h20, val); /* ROM base */
 540                 do_spi(8'h00, val);
 541                 do_spi(8'h00, val);
 542                 _spi_cs = 1;
 543                 #(SPI_HCLOCK*4);
 544                 _spi_cs = 0;
 545                 do_spi(`BB_WRITE | `BB_REG_MEM_BASE | 3, val);/
 546                 i = 0;
 547                 repeat(rom_size) begin
 548                         do_spi(rom[i], val);
 549                         i = i+1;
 550                         if ((i % 1024) == 0)
 551                           $display("%h", i);
 552                 end
 553                 _spi_cs = 1;
 554                 #(SPI_HCLOCK*4);
 555
 556                 $display("RAM dump...");
 557                 $display("%h %h %h %h %h %h %h %h",
 558                          sval[0], sval[1], sval[2], sval[3],
 559                          sval[4], sval[5], sval[6], sval[7]);
 560
 561                 /* Start the scope */
 562                 _spi_cs = 0;
 563                 do_spi(`BB_WRITE | `BB_REG_SCOPE_BASE, val);
 564                 do_spi(8'h02, val);
 565                 _spi_cs = 1;
 566                 #(SPI_HCLOCK*4);
 567
 568                 /* Un-reset CPU */
 569                 _spi_cs = 0;
 570                 do_spi(`BB_WRITE | `BB_REG_CTRL_BASE | 2, val);
 571                 do_spi(8'h01, val);
 572                 _spi_cs = 1;
 573                 #(SPI_HCLOCK*4);
 574
 575                 /* Set breakpoint */
 576                 _spi_cs = 0;
 577                 do_spi(`BB_WRITE | `BB_AUTOINC | `BB_REG_CPU_BASE | 8, val);
 578                 do_spi(8'h00, val);
 579                 do_spi(8'h10, val);
 580                 do_spi(8'h22, val);
 581                 _spi_cs = 1;
 582                 #(SPI_HCLOCK*4);
 583
 584                 /* Run CPU interface */
 585                 _spi_cs = 0;
 586                 do_spi(`BB_WRITE | `BB_REG_CPU_BASE | 6, val);
 587                 do_spi(8'h42, val); /* RUN + BKEN */
 588                 _spi_cs = 1;
 589                 #(SPI_HCLOCK*4);
 590
 591                 repeat(10) begin
 592                         /* Get CPU status */
 593                         _spi_cs = 0;
 594                         do_spi(`BB_WRITE | `BB_REG_CPU_BASE | 7, val);
 595                         do_spi(8'hff, val);
 596                         do_spi(8'hff, val);
 597                         _spi_cs = 1;
 598                         #(SPI_HCLOCK*4);
 599                         $display("CPU Stat: %h", val);
 600                 end
 601 `endif
 602
 603 `ifdef foo
 604                 $display("Steps:");
 605                 repeat(100) begin
 606                         /* Step CPU interface */
 607                         _spi_cs = 0;
 608                         do_spi(`BB_WRITE | `BB_REG_CPU_BASE | 6, val);
 609                         do_spi(8'h82, val); /* RUN + STEP */
 610                         _spi_cs = 1;
 611                         #(SPI_HCLOCK*4);
 612
 613                         /* We shall wait for cycle to complete but we know
 614                          * how slow our SPI is ...
 615                          */
 616                         /* Read latches */
 617                         _spi_cs = 0;
 618                         do_spi(`BB_AUTOINC | `BB_REG_CPU_BASE, val);
 619                         do_spi(8'hff, val);
 620                         do_spi(8'hff, sval[0]);
 621                         do_spi(8'hff, sval[1]);
 622                         do_spi(8'hff, sval[2]);
 623                         do_spi(8'hff, sval[3]);
 624                         do_spi(8'hff, sval[4]);
 625                         do_spi(8'hff, sval[5]);
 626                         _spi_cs = 1;
 627                         #(SPI_HCLOCK*4);
 628                         $display("RW:%b U:%b L:%b ADDR: %h DATA: %h",
 629                                  sval[5][0], sval[5][1], sval[5][2],
 630                                  { sval[0], sval[1], sval[2] },
 631                                  { sval[3], sval[4] });
 632                 end
 633 `endif
 634
 635 `ifdef foo
 636
 637                 $display("Reading 0x1020 via SPI initiaed read cycle:");
 638
 639                 /* Read value at 0x1020 */
 640                 _spi_cs = 0;
 641                 do_spi(8'hc8, val); /* b001_000 */
 642                 do_spi(8'h00, val);
 643                 do_spi(8'h10, val);
 644                 do_spi(8'h20, val);
 645                 do_spi(8'haa, val);
 646                 do_spi(8'h55, val);
 647                 do_spi(8'h01, val); /* _uds = 0, _lds = 0, r_w = 1 */
 648                 do_spi(8'h04, val); /* ctrl: cycle */
 649                 _spi_cs = 1;
 650                 #(SPI_HCLOCK*4);
 651
 652                 /* Here too, shall wait but heh ! */
 653
 654                 /* Read latches */
 655                 _spi_cs = 0;
 656                 do_spi(8'h48, val); /* b001_000 */
 657                 do_spi(8'hff, val);
 658                 do_spi(8'hff, sval[0]);
 659                 do_spi(8'hff, sval[1]);
 660                 do_spi(8'hff, sval[2]);
 661                 do_spi(8'hff, sval[3]);
 662                 do_spi(8'hff, sval[4]);
 663                 do_spi(8'hff, sval[5]);
 664                 _spi_cs = 1;
 665                 #(SPI_HCLOCK*4);
 666                 $display("RW:%b U:%b L:%b ADDR: %h DATA: %h",
 667                          sval[5][0], sval[5][1], sval[5][2],
 668                          { sval[0], sval[1], sval[2] },
 669                          { sval[3], sval[4] });
 670
 671                 /* Read memory from 0x1000 using mem SPI */
 672                 _spi_cs = 0;
 673                 do_spi(8'he0, val); /* b100_000 */
 674                 do_spi(8'h00, val);
 675                 do_spi(8'h10, val);
 676                 do_spi(8'h00, val);
 677                 _spi_cs = 1;
 678                 #(SPI_HCLOCK*4);
 679                 _spi_cs = 0;
 680                 do_spi(8'h23, val); /* b100_000 */
 681                 do_spi(8'hff, val);
 682                 do_spi(8'hff, val); /* add. dummy cycle for reads */
 683                 do_spi(8'hff, sval[0]);
 684                 do_spi(8'hff, sval[1]);
 685                 do_spi(8'hff, sval[2]);
 686                 do_spi(8'hff, sval[3]);
 687                 do_spi(8'hff, sval[4]);
 688                 do_spi(8'hff, sval[5]);
 689                 do_spi(8'hff, sval[6]);
 690                 do_spi(8'hff, sval[7]);
 691                 _spi_cs = 1;
 692                 #(SPI_HCLOCK*4);
 693
 694                 $display("RAM dump...");
 695                 $display("%h %h %h %h %h %h %h %h",
 696                          sval[0], sval[1], sval[2], sval[3],
 697                          sval[4], sval[5], sval[6], sval[7]);
 698
 699 `endif
 700
 701 `ifdef foo
 702                 $display("Run....");
 703
 704                 /* Run CPU interface */
 705                 _spi_cs = 0;
 706                 do_spi(8'h8e, val); /* b001_110 */
 707                 do_spi(8'h02, val); /* RUN */
 708                 _spi_cs = 1;
 709                 #(SPI_HCLOCK*4);
 710 `endif
 711                 /* Wait a bit and stop the scope */
 712                 #4000000;
 713
 714 `ifdef foo
 715                 _spi_cs = 0;
 716                 do_spi(`BB_WRITE | `BB_REG_SCOPE_BASE, val);
 717                 do_spi(8'h00, val);
 718                 _spi_cs = 1;
 719                 #(SPI_HCLOCK*4);
 720 `endif
 721
 722 `ifdef foo
 723                 /* Dump scope output */
 724                 _spi_cs = 0;
 725                 do_spi(8'h3c, val);
 726                 do_spi(8'hff, val);
 727                 i = 0;
 728                 repeat(2048) begin
 729                         do_spi(8'hff, sval[0]);
 730                         do_spi(8'hff, sval[1]);
 731                         do_spi(8'hff, sval[2]);
 732                         do_spi(8'hff, sval[3]);
 733                         do_spi(8'hff, sval[4]);
 734                         do_spi(8'hff, sval[5]);
 735                         do_spi(8'hff, sval[6]);
 736                         do_spi(8'hff, sval[7]);
 737                         $display("%h %h %h %h %h %h %h %h",
 738                                  sval[0], sval[1], sval[2], sval[3],
 739                                  sval[4], sval[5], sval[6], sval[7]);
 740                 end
 741                 _spi_cs = 1;
 742                 #(SPI_HCLOCK*4);
 743 `endif
 744         end
 745
 746 endmodule