fpga/sim_mouse.v

   1 `timescale 1ns / 100ps
   2
   3 module sim_mouse(inout clk, inout dat);
   4 `define CLK_HALF        5000    /* faster sim, should be more like 50000 */
   5
   6         reg aclk;
   7         reg adat;
   8         reg [7:0] cmd;
   9
  10         task do_send;
  11                 input [7:0]     d;
  12                 output          ok;
  13                 reg [10:0]      sr;
  14                 reg             p;
  15                 integer         i;
  16                 begin
  17                         $display("sim_mouse: send %x", d);
  18
  19                         p = ~(d[0] ^ d[1] ^ d[2] ^ d[3] ^
  20                               d[4] ^ d[5] ^ d[6] ^ d[7]);
  21                         sr = { 1'b1, p, d, 1'b0 };
  22                         aclk = 0;
  23                         adat = 0;
  24                         ok = 1;
  25                         i = 11;
  26                         while(i > 0 && ok) begin
  27                                 if (clk == 0) begin
  28                                         $display("Mouse: Clock low, aborting send");
  29                                         ok = 0;
  30                                 end else begin
  31                                         adat = ~sr[0];
  32                                         #`CLK_HALF aclk = 1;
  33                                         #`CLK_HALF aclk = 0;
  34                                         #1;
  35                                         sr = { 1'b0, sr[10:1] };
  36                                         i = i - 1;
  37                                 end
  38                         end
  39                         aclk = 0;
  40                         adat = 0;
  41                         #`CLK_HALF;
  42                         #`CLK_HALF;
  43                 end
  44         endtask
  45
  46         task do_receive;
  47                 output [7:0]    d;
  48                 output          ok;
  49                 reg [10:0]      sr;
  50                 reg             p;
  51                 integer         i;
  52                 begin
  53                         aclk = 0;
  54                         adat = 0;
  55                         sr = 0;
  56                         wait(dat == 0);
  57                         wait(clk != 0);
  58                         ok = 1;
  59                         i = 10;
  60                         while(i > 0 && ok) begin
  61                                 if (clk == 0) begin
  62                                         $display("Mouse: Clock low, aborting receive");
  63                                         ok = 0;
  64                                 end else begin
  65                                         #`CLK_HALF aclk = 1;
  66                                         #`CLK_HALF aclk = 0;
  67                                         #1;
  68                                         sr = { dat != 0, sr[10:1] };
  69                                         i = i - 1;
  70                                 end
  71                         end // while (i > 0 && ok)
  72                         adat = 1;
  73                         #`CLK_HALF aclk = 1;
  74                         #`CLK_HALF aclk = 0;
  75                         adat = 0;
  76 //                      $display("rx shift final: %b", sr);
  77                         aclk = 0;
  78                         adat = 0;
  79                         d = sr[8:1];
  80                         #`CLK_HALF;
  81                         #`CLK_HALF;
  82                         $display("sim_mouse:  got %x ok=%b", d, ok);
  83         end
  84         endtask
  85
  86         pullup(clk);
  87         pullup(dat);
  88
  89         assign clk = aclk ? 1'b0 : 1'bz;
  90         assign dat = adat ? 1'b0 : 1'bz;
  91
  92         reg ok;
  93
  94         always@(clk, dat) begin
  95                 while (clk == 0) begin
  96                         #`CLK_HALF;
  97                         if (clk == 0) begin
  98                                 #`CLK_HALF;
  99                                 if (clk == 0) begin
 100                                         do_receive(cmd, ok);
 101                                         if (ok) begin
 102                                                 if (cmd == 8'hf4) begin
 103                                                         do_send(8'hfa, ok);
 104                                                 end else if (cmd == 8'hff) begin
 105                                                         if (ok)
 106                                                           do_send(8'haa, ok);
 107                                                         if (ok)
 108                                                           do_send(8'h00, ok);
 109                                                 end
 110                                         end
 111                                 end
 112                         end
 113                 end
 114         end
 115
 116         initial begin
 117                 aclk = 0;
 118                 adat = 0;
 119                 #`CLK_HALF;
 120                 #`CLK_HALF;
 121                 #`CLK_HALF;
 122                 #`CLK_HALF;
 123                 do_send(8'haa, ok);
 124                 do_send(8'h00, ok);
 125                 #6000000;
 126                 do_send(8'h00, ok);
 127                 do_send(8'h02, ok);
 128                 do_send(8'h00, ok);
 129                 #1000000;
 130                 do_send(8'h00, ok);
 131                 do_send(8'h02, ok);
 132                 do_send(8'h00, ok);
 133                 #1000000;
 134                 do_send(8'h00, ok);
 135                 do_send(8'h00, ok);
 136                 do_send(8'h02, ok);
 137         end
 138 endmodule
 139