3 input mclk, /* 4.433619 Mhz input */
4 output sysclk16, /* System clock outputs */
5 output sysclk33, /* System clock outputs NOT IMPLEMENTED, running at 16.6 */
6 output pixclk /* Pixel clock */
12 IBUFG mclk_buf( .I(mclk), .O(pll_mclk));
14 /* Generate 16.6 for the DLL cpu*/
17 .CLKDV_DIVIDE(2.0), // Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5,
18 // 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
19 .CLKFX_DIVIDE(4), // Can be any integer from 1 to 32
20 .CLKFX_MULTIPLY(15), // Can be any integer from 2 to 32
21 .CLKIN_DIVIDE_BY_2("FALSE"), // TRUE/FALSE to enable CLKIN divide by two feature
22 .CLKIN_PERIOD(225.0), // Specify period of input clock
23 .CLKOUT_PHASE_SHIFT("NONE"), // Specify phase shift of NONE, FIXED or VARIABLE
24 .CLK_FEEDBACK("NONE"), // Specify clock feedback of NONE, 1X or 2X
25 .DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"), // SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or an integer from 0 to 15
26 .DFS_FREQUENCY_MODE("LOW"), // HIGH or LOW frequency mode for frequency synthesis
27 .DLL_FREQUENCY_MODE("LOW"), // HIGH or LOW frequency mode for DLL
28 .DUTY_CYCLE_CORRECTION("TRUE"), // Duty cycle correction, TRUE or FALSE
29 .FACTORY_JF(16'hC080), // FACTORY JF values
30 .PHASE_SHIFT(0), // Amount of fixed phase shift from -255 to 255
31 .STARTUP_WAIT("FALSE") // Delay configuration DONE until DCM LOCK, TRUE/FALSE
35 .CLKFX(pll_c16), // DCM CLK synthesis out (M/D)
36 .CLKIN(pll_mclk) // Clock input (from IBUFG, BUFG or DCM)
39 /* Generate a rough 25.1Mhz for the video */
42 .CLKDV_DIVIDE(3.0), // Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5,
43 // 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
44 .CLKFX_DIVIDE(3), // Can be any integer from 1 to 32
45 // .CLKFX_MULTIPLY(16), // Can be any integer from 2 to 32
46 .CLKFX_MULTIPLY(17), // Can be any integer from 2 to 32
47 .CLKIN_DIVIDE_BY_2("FALSE"), // TRUE/FALSE to enable CLKIN divide by two feature
48 .CLKIN_PERIOD(225.0), // Specify period of input clock
49 .CLKOUT_PHASE_SHIFT("NONE"), // Specify phase shift of NONE, FIXED or VARIABLE
50 .CLK_FEEDBACK("NONE"), // Specify clock feedback of NONE, 1X or 2X
51 .DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"), // SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or an integer from 0 to 15
52 .DFS_FREQUENCY_MODE("LOW"), // HIGH or LOW frequency mode for frequency synthesis
53 .DLL_FREQUENCY_MODE("LOW"), // HIGH or LOW frequency mode for DLL
54 .DUTY_CYCLE_CORRECTION("TRUE"), // Duty cycle correction, TRUE or FALSE
55 .FACTORY_JF(16'hC080), // FACTORY JF values
56 .PHASE_SHIFT(0), // Amount of fixed phase shift from -255 to 255
57 .STARTUP_WAIT("FALSE") // Delay configuration DONE until DCM LOCK, TRUE/FALSE
61 .CLKFX(pll_c25), // DCM CLK synthesis out (M/D)
62 .CLKIN(pll_mclk) // Clock input (from IBUFG, BUFG or DCM)
65 /* Global clock buffers */
66 BUFG clk33_buf( .I(pll_c16), .O(sysclk33)); /* NOT IMPL. RUNNING AT 16Mhz */
67 BUFG clk16_buf( .I(pll_c16), .O(sysclk16));
69 /* Temporarily assign pixclock to 33Mhz, will fix later */
70 BUFG pixclk_buf( .I(pll_c25), .O(pixclk));