fpga/sim_bench.v

   1 `timescale 1ns / 100ps
   2
   3 module main();
   4
   5         /* Interface between FPGA and other siumulated components */
   6
   7         /* m68k interface */
   8         wire [15:0]     cpu_data;
   9         wire [23:1]     cpu_address;
  10         wire [2:0]      _cpu_ipl;
  11         wire            _cpu_as;
  12         wire            _cpu_uds;
  13         wire            _cpu_lds;
  14         wire            cpu_r_w;
  15         wire            _cpu_dtack;
  16         wire            _cpu_reset;
  17         wire            cpu_clk;
  18
  19         /* SRAM interface */
  20         wire [15:0]     ram_data;
  21         wire [19:1]     ram_address;
  22         wire [3:0]      _ram_ce;
  23         wire            _ram_bhe;
  24         wire            _ram_ble;
  25         wire            _ram_we;
  26         wire            _ram_oe;
  27
  28         /* RS232 pins */
  29         wire            rxd;
  30         wire            txd;
  31         wire            cts;
  32         wire            rts;
  33
  34         /* Joystick ports */
  35         wire [5:0]      _joy1;
  36         wire [5:0]      _joy2;
  37
  38         /* PS2 ports */
  39         wire            msdat;
  40         wire            msclk;
  41         wire            kbddat;
  42         wire            kbdclk;
  43
  44         /* Video pins */
  45         wire            _hsync;
  46         wire            _vsync;
  47         wire [3:0]      red;
  48         wire [3:0]      green;
  49         wire [3:0]      blue;
  50
  51         /* Audio pins */
  52         wire            left;
  53         wire            right;
  54
  55         /* System pins */
  56         wire            mclk; /* Note: Ignored in sim */
  57         wire            pwrled;
  58         wire            init_b;
  59         wire            _15khz;
  60         wire            gpio;
  61         wire            scsi_hshake;
  62         wire            nmi;
  63
  64         /* SPI pins */
  65         wire            _spi_cs;
  66         wire            sdi;
  67         wire            sdo;
  68         wire            sck;
  69
  70         /* Unused CPU output pins */
  71         wire [2:0]      cpu_fc;
  72         wire            _cpu_bg;
  73
  74         /* Instanciate 4 SRAM modules */
  75         sim_sram512x16 ram0(.addr(ram_address),
  76                             .data(ram_data),
  77                             ._cs(_ram_ce[0]),
  78                             ._oe(_ram_oe),
  79                             ._we(_ram_we),
  80                             ._ub(_ram_bhe),
  81                             ._lb(_ram_ble));
  82
  83         sim_sram512x16 ram1(.addr(ram_address),
  84                             .data(ram_data),
  85                             ._cs(_ram_ce[1]),
  86                             ._oe(_ram_oe),
  87                             ._we(_ram_we),
  88                             ._ub(_ram_bhe),
  89                             ._lb(_ram_ble));
  90
  91         sim_sram512x16 ram2(.addr(ram_address),
  92                             .data(ram_data),
  93                             ._cs(_ram_ce[2]),
  94                             ._oe(_ram_oe),
  95                             ._we(_ram_we),
  96                             ._ub(_ram_bhe),
  97                             ._lb(_ram_ble));
  98
  99         sim_sram512x16 ram3(.addr(ram_address),
 100                             .data(ram_data),
 101                             ._cs(_ram_ce[3]),
 102                             ._oe(_ram_oe),
 103                             ._we(_ram_we),
 104                             ._ub(_ram_bhe),
 105                             ._lb(_ram_ble));
 106
 107         /* Instanciate CPU. Lotsa stuff not wired on Minimig */
 108         m68k cpu0(.clk(cpu_clk),
 109                  .fc(cpu_fc),
 110                  .a(cpu_address),
 111                  ._as(_cpu_as),
 112                  ._uds(_cpu_uds),
 113                  ._lds(_cpu_lds),
 114                  .r_w(cpu_r_w),
 115                  ._dtack(_cpu_dtack),
 116                  .d(cpu_data),
 117                  ._ipl(_cpu_ipl),
 118                  ._avec(1'b1),
 119                  ._br(1'b1),
 120                  ._bg(_cpu_bg),
 121                  ._berr(1'b1),
 122                  ._reset(_cpu_reset),
 123                  ._halt(1'b1));
 124
 125         pullup(_cpu_reset);
 126
 127       defparam cpu.turbo = 1;
 128 //      defparam cpu.log_flags = 0;
 129 //      defparam cpu.log_flags = 'hff;
 130
 131         /* Instanciate the FPGA */
 132         minimigmac minimigmac0(.cpu_data(cpu_data),
 133                                .cpu_address(cpu_address),
 134                                ._cpu_ipl(_cpu_ipl),
 135                                ._cpu_uds(_cpu_uds),
 136                                ._cpu_lds(_cpu_lds),
 137                                ._cpu_as(_cpu_as),
 138                                .cpu_r_w(cpu_r_w),
 139                                ._cpu_dtack(_cpu_dtack),
 140                                ._cpu_reset(_cpu_reset),
 141                                .cpu_clk(cpu_clk),
 142                                .ram_data(ram_data),
 143                                .ram_address(ram_address),
 144                                ._ram_ce(_ram_ce),
 145                                ._ram_bhe(_ram_bhe),
 146                                ._ram_ble(_ram_ble),
 147                                ._ram_we(_ram_we),
 148                                ._ram_oe(_ram_oe),
 149                                .rxd(rxd),
 150                                .txd(txd),
 151                                .cts(cts),
 152                                .rts(rts),
 153                                ._joy1(_joy1),
 154                                ._joy2(_joy2),
 155                                .msdat(msdat),
 156                                .msclk(msclk),
 157                                .kbddat(kbddat),
 158                                .kbdclk(kbdclk),
 159                                ._hsync(_hsync),
 160                                ._vsync(_vsync),
 161                                .red(red),
 162                                .green(green),
 163                                .blue(blue),
 164                                .left(left),
 165                                .right(right),
 166                                .mclk(mclk),
 167                                .pwrled(pwrled),
 168                                .init_b(init_b),
 169                                ._15khz(_15khz),
 170                                .gpio(gpio),
 171                                .nmi(nmi),
 172                                .scsi_hshake(scsi_hshake),
 173                                ._spi_cs(_spi_cs),
 174                                .sdi(sdi),
 175                                .sdo(sdo),
 176                                .sck(sck));
 177
 178         sim_pic pic0(.sdo(sdi),
 179                      .sdi(sdo),
 180                      .sck(sck),
 181                      ._spi_cs(_spi_cs),
 182                      .scsi_hshake(scsi_hshake),
 183                      .nmi(nmi));
 184
 185         sim_mouse mouse0(.clk(msclk), .dat(msdat));
 186         sim_kbd kbd0(.clk(kbdclk), .dat(kbddat));
 187
 188         integer rom_file;
 189         integer rom_size;
 190
 191         initial begin
 192                 $dumpfile("sim_bench.vcd");
 193                 $dumpvars(0,minimigmac0);
 194                 $dumpvars(0,ram0);
 195                 $dumpvars(0,ram1);
 196                 $dumpvars(0,ram2);
 197                 $dumpvars(0,ram3);
 198                 $dumpvars(0,pic0);
 199                 $dumpvars(0,cpu0);
 200                 $dumpvars(0,mouse0);
 201
 202                 $display("Loading ROM...");
 203                 rom_file = $fopenr("rom.bin");
 204                 rom_size = $fread(ram2.mem, rom_file, 0);
 205                 $fclose(rom_file);
 206                 $display("Loaded 0x%h bytes", rom_size);
 207                 $display("ram[841]=%h", ram2.mem['h841]);
 208                 $display("Disabling mem test");
 209                 ram0.mem['h2a2/2] = 'h0040;
 210                 ram0.mem['h2a4/2] = 'h0000;
 211                 $display("Disabling boot beep & clr screen etc...");
 212                 ram2.mem['hf4/2] = 'h4e71;
 213                 ram2.mem['hf6/2] = 'h4e71;
 214                 ram2.mem['hea/2] = 'h4e71;
 215                 ram2.mem['hec/2] = 'h4e71;
 216                 ram2.mem['h34/2] = 'h4e71;
 217                 ram2.mem['h36/2] = 'h4e71;
 218                 ram2.mem['h38/2] = 'h4e71;
 219                 ram2.mem['h3a/2] = 'h4e71;
 220                 ram2.mem['h3c/2] = 'h4e71;
 221                 ram2.mem['h3e/2] = 'h4e71;
 222                 ram2.mem['h40/2] = 'h4e71;
 223                 /* checksum & test memory replaced with
 224                  * movea.l #memsize, a5 and beq->bra
 225                  */
 226                 ram2.mem['h12a/2] = 'h2a7c;
 227                 ram2.mem['h12c/2] = 'h0020;
 228                 ram2.mem['h12e/2] = 'h0000;
 229                 ram2.mem['h130/2] = 'h4e71;
 230                 ram2.mem['h132/2] = 'h6000;
 231                 ram0.mem['h108/2] = 'h0020; /* memtop */
 232                 ram0.mem['h10a/2] = 'h0000;
 233                 #50000000;
 234                 $finish;
 235         end
 236 endmodule