fpga/ctrl.v

   1 /* RW: ID registers */
   2 `define CTRL_REG_FPGA_ID        0
   3 `define CTRL_REG_FPGA_VERSION   1
   4
   5 /* WO: Global control register */
   6 `define CTRL_REG_GCTRL          2
   7 `define     GCTRL_CPU_UNRESET_BIT       0
   8
   9 /* RO: PS2 Mouse Debug */
  10 `define CTRL_REG_PS2M_DBG0      3
  11 `define CTRL_REG_PS2M_DBG1      4
  12
  13 /* RO: PS2 Kbd Debug */
  14 `define CTRL_REG_PS2K_DBG0      5
  15 `define CTRL_REG_PS2K_DBG1      6
  16
  17 module ctrl
  18 (
  19         input                           sysclk,
  20         input                           reset,
  21
  22         /* Backbus interface */
  23         input [5:0]                     bb_addr,
  24         input [7:0]                     bb_wdata,
  25         output [7:0]                    bb_rdata,
  26         input                           bb_strobe,
  27         input                           bb_wr,
  28
  29         /* Debug stuff */
  30         input [15:0]                    ps2m_dbg,
  31         input [15:0]                    ps2k_dbg,
  32
  33         /* Generated control signals */
  34         output                          cpu_reset
  35 );
  36         /* Latched registers */
  37         reg [7:0]                       gctrl;
  38
  39         assign cpu_reset = ~gctrl[`GCTRL_CPU_UNRESET_BIT];
  40
  41         assign bb_rdata = (bb_addr[2:0] == `CTRL_REG_FPGA_ID) ? 8'h42 :
  42                           (bb_addr[2:0] == `CTRL_REG_FPGA_VERSION) ? 8'h01 :
  43                           (bb_addr[2:0] == `CTRL_REG_GCTRL) ? gctrl :
  44                           (bb_addr[2:0] == `CTRL_REG_PS2M_DBG0) ? ps2m_dbg[15:8] :
  45                           (bb_addr[2:0] == `CTRL_REG_PS2M_DBG1) ? ps2m_dbg[7:0] :
  46                           (bb_addr[2:0] == `CTRL_REG_PS2K_DBG0) ? ps2k_dbg[15:8] :
  47                           (bb_addr[2:0] == `CTRL_REG_PS2K_DBG1) ? ps2k_dbg[7:0] :
  48                           0;
  49
  50         /* Register interface */
  51         always@(posedge sysclk or posedge reset) begin
  52                 if (reset) begin
  53                         gctrl <= 0;
  54                 end else begin
  55                         if (bb_strobe && bb_wr) begin
  56                                 case(bb_addr[2:0])
  57                                         `CTRL_REG_GCTRL:
  58                                           gctrl <= bb_wdata;
  59                                 endcase
  60                         end
  61                 end
  62         end
  63 endmodule
  64
  65
  66
  67
  68