--- /dev/null
+; Radeon registers
+; Contributors: Jeremy Kerr <jk@ozlabs.org>
+;
+; Adapted from the xorg ati driver
+;
+
+; radeon_reg.h
+[FP_GEN_CNTL]
+name: Radeon Flatpanel Generic Control
+width: 32
+field: 1<<0 Flatpanel (TMDS) on
+field: 1<<1 Blank enable
+field: 1<<2 TMDS enable
+field: 1<<3 Panel format
+field: 1<<7 Enable TMDS
+field: 1<<8 Detect sense
+field: 3<<10 R200 source select
+value: 0 CRTC1
+value: 1 CRTC2
+value: 2 RMX
+value: 3 TRANS
+field: 1<<13 Radeon FP select
+value: 0 CRTC1
+value: 1 CRTC2
+field: 1<<15 CRTC don't shadow HPAR
+field: 1<<16 CRTC don't shadow VPAR
+field: 1<<17 CRTC don't shadow HEND
+field: 1<<18 CRTC use shadow VEND
+field: 1<<20 RMX HVSYNC control enable
+field: 1<<21 DFP sync select
+field: 1<<22 CRTC lock 8DOT
+field: 1<<23 CRT sync select
+field: 1<<24 use shadow enable
+field: 1<<26 CRT sync alternate
+
+; radeon_reg.h
+[FP2_GEN_CNTL]
+name: Radeon Secondary Flatpanel Generic Control
+width: 32
+field: 1<<1 Blank enable
+field: 1<<2 Flatpanel on
+field: 1<<3 Panel format
+field: 3<<10 R200 source select
+value: 0 CRTC1
+value: 1 CRTC2
+value: 2 RMX
+field: 3<<13 Radeon source select
+value: 0 CRTC1
+value: 1 CRTC2
+field: 1<<16 FP_POL
+field: 1<<17 LP_POL
+field: 1<<18 SCK_POL
+field: 7<<19 LCD control
+field: 1<<22 PAD_FLOP enable
+field: 1<<23 CRC enable
+field: 1<<24 CRC read enable
+field: 1<<25 DVO enable
+field: 1<<26 DVO rate select SDR
+
+; radeon_reg.h
+[LVDS_GEN_CNTL]
+name: Radeon LVDS Generic Control
+width: 32
+field: 1<<0 LVDS On
+field: 1<<1 Display DIS
+field: 1<<2 Panel type
+field: 1<<3 Panel format
+field: 1<<7 Enable
+field: 1<<18 Digital on
+field: 1<<19 Backlight on
+field: 1<<23 Select CRTC2
+
+; radeon_reg.h
+[TMDS_TRANSMITTER_CNTL]
+name: Radeon TMDS Transmitter Control
+width: 32
+field: 1<<0 PLL enable
+field: 1<<1 PLL reset
+