Minor changes to register class

Signed-off-by: Jeremy Kerr <jk@ozlabs.org>

diff --git a/bitfield b/bitfield
index 32a0405648b0d4dade7caff3b4a1421facf704e5..3651677f86c29ab8a90d9a67df14fa086ffa4503 100644 (file)
--- a/bitfield
+++ b/bitfield
@@ -77,13 +77,15 @@ class register:
                self.width = width
                self.fields = []
 
-       def add_field(self, field,):
+       def add_field(self, field):
                self.fields.append(field)
 
        def decode(self, value, ignore_zero):
                field_width = (self.width + 3) / 4
                name_width = max(map(lambda f: len(f.name), self.fields))
+
                str = "0x%0*lx [%d]\n" % (field_width, value, value)
+
                for field in self.fields:
                        v = field.mask(self.width, value);
                        if ignore_zero and v == 0: