1 ; Definitions for the PowerPC architecture
4 ; Michael Neuling <mikey@neuling.org>
7 ; PowerPC® Microprocessor Family:
8 ; The Programming Environments Manual for
9 ; 32 and 64-bit Microprocessors
11 ; http://www.power.org/resources/downloads/PowerISA_203.Public.pdf
14 ; Section 2.3.1 Machine State Register (MSR)
16 name: PowerPC Machine State Register
17 field: 0 64-bit mode (SF)
20 field: 2 Exception 64-bit mode
21 field: 3 Hypervisor State (HV)
22 field: 45 Power Management Enable (POW)
23 field: 47 Little-Endian Exception Mode (ILE)
24 field: 48 External Interrupt Enable (EE)
25 field: 49 Problem State (PR)
26 value: 0 privileged state
27 value: 1 problem state
28 field: 50 Floating-Point Available (FP)
29 field: 51 Machine Check Interrupt Enable (ME)
30 field: 52,55 Floating-Point Exception Mode (FE)
31 value: 0 ignore exceptions
32 value: 1 imprecise nonrecoverable
33 value: 2 imprecise recoverable
35 field: 53 Single-Step Trace Enable (SE)
36 field: 54 Branch Trace Enable (BE)
37 field: 58 Instruction Relocate (IR)
38 field: 59 Data Relocate (DR)
39 field: 61 Performance Monitor Mark (PMM)
40 field: 62 Recoverable Interrupt (RI)
41 field: 63 Little-Endian Mode (LE)
43 value: 1 little-endian
45 ; Section 8, Instruction slbmte
47 name: PowerPC SLB ESID Entry
48 field: 0:35 Effective segment ID (ESID)
52 ; Section 8, Instruction slbmte
54 name: PowerPC SLB VSID Entry
55 field: 0:1 Segment size selector (B)
60 field: 2:51 Virtual segment ID (VSID)
61 field: 52 Supervisor state storage key (Ks)
62 field: 53 Problem state storage key (Kp)
63 field: 55,58,59 Virtual page size selector
64 value: 0 4KB (Unless PTE specifies 64KB) (MPS)
65 value: 5 64KB (Provided PTE specifies 64KB) (MPS)
66 field: 54 No-execute segment (N)
69 value: 1 little-endian