+; Definitions for the PowerPC architecture
+;
+; Contributors:
+; Michael Neuling <mikey@neuling.org>
+
+[MSR]
+name: PowerPC Machine State Register
+field: 0 64-bit mode (SF)
+value: 0 32-bit mode
+value: 1 64-bit mode
+field: 3 Hypervisor State (HV)
+field: 48 External Interrupt Enable (EE)
+field: 49 Problem State (PR)
+value: 0 privileged state
+value: 1 problem state
+field: 50 Floating-Point Available (FP)
+field: 51 Machine Check Interrupt Enable (ME)
+field: 52,55 Floating-Point Exception Mode (FE)
+value: 0 ignore exceptions
+value: 1 imprecise nonrecoverable
+value: 2 imprecise recoverable
+value: 3 precise
+field: 53 Single-Step Trace Enable (SE)
+field: 54 Branch Trace Enable (BE)
+field: 58 Instruction Relocate (IR)
+field: 59 Data Relocate (DR)
+field: 61 Performance Monitor Mark (PMM)
+field: 62 Recoverable Interrupt (RI)
+field: 63 Little-Endian Mode (LE)
+value: 0 big-endian
+value: 1 little-endian
+
+[SLB_E]
+name: PowerPC SLB ESID Entry
+field: 0:35 Effective segment ID (ESID)
+field: 36 Valid (V)
+field: 52:63 Index
+
+[SLB_V]
+name: PowerPC SLB VSID Entry
+field: 0:1 Segment size selector (B)
+value: 0 256MB
+value: 1 1TB
+value: 2 reserved
+value: 3 reserved
+field: 2:51 Virtual segment ID (VSID)
+field: 52 Supervisor state storage key (Ks)
+field: 53 Problem state storage key (Kp)
+field: 55,58,59 Virtual page size selector
+value: 0 4KB (Unless PTE specifies 64KB) (MPS)
+value: 5 64KB (Provided PTE specifies 64KB) (MPS)
+field: 54 No-execute segment (N)
+field: 56 Class (C)
+value: 0 big-endian
+value: 1 little-endian
+