11 #define printf printf_tiny
13 /* Sector buffer. Shared globally to save space on PIC
15 * XXX In this file to work around a missing bank select problem
17 unsigned char secbuf[512];
19 static char hex[] = {'0','1','2','3','4','5','6','7','8','9','a','b','c',
22 /* Temp buffer used for tests */
23 static unsigned char c[10];
25 static unsigned char load_file(char *name, unsigned long addr)
29 unsigned char *ptr = secbuf;
32 size = fat_open(name);
34 printf("File %s not found !\n", name);
40 do_spi(BB_WRITE | BB_AUTOINC | BB_REG_MEM_BASE);
41 do_spi((addr >> 16) & 0xff);
42 do_spi((addr >> 8) & 0xff);
43 do_spi((addr ) & 0xff);
49 /* read sector if 512 (64*8) bytes done */
50 if ((t & 0x3f) == 0) {
56 if (!fat_file_read()) {
57 printf("Reading failed !\n");
61 do_spi(BB_WRITE | BB_REG_MEM_BASE | 3);
65 /* send data in packets of 8 bytes */
76 /* read next sector if 512 (64*8) bytes done */
77 if ((t & 0x3f) == 0) {
79 fat_file_next_sector();
91 static unsigned char configure_fpga(void)
95 unsigned char *ptr = secbuf;
98 /* Reset FGPA configuration sequence */
101 // now wait for INIT to go high
105 printf("FPGA init is NOT high!\n");
110 printf("FPGA done is high before configuration!\n");
114 /* Open bitstream file */
115 size = fat_open("MIMIGMACBIN");
117 printf("No FPGA configuration file found!\n");
122 /* Send all bytes to FPGA in loop */
126 /* read sector if 512 (64*8) bytes done */
127 if ((t & 0x3f) == 0) {
133 if (!fat_file_read()) {
134 printf("Reading failed !\n");
140 /* send data in packets of 8 bytes */
141 shift_fpga(*(ptr++));
142 shift_fpga(*(ptr++));
143 shift_fpga(*(ptr++));
144 shift_fpga(*(ptr++));
145 shift_fpga(*(ptr++));
146 shift_fpga(*(ptr++));
147 shift_fpga(*(ptr++));
148 shift_fpga(*(ptr++));
151 /* read next sector if 512 (64*8) bytes done */
153 fat_file_next_sector();
154 if ((t & 0x7ff) == 0)
171 /* check if DONE is high */
187 printf("FPGA done is NOT high!\n");
191 static void print_latches(void)
193 printf(" RW:%d U:%d L:%d ADDR: %x %x %x DATA: %x %x\n",
197 c[0], c[1], c[2], c[3], c[4]);
201 static void dump_scope(void)
205 /* Dump scope output */
207 do_spi(BB_AUTOINC | BB_REG_SCOPE_BASE | 2);
211 printf("sample count: %x %x\n", c[0], c[1]);
214 do_spi(BB_WRITE | BB_REG_SCOPE_BASE | 4);
219 do_spi(BB_REG_SCOPE_BASE | 4);
221 // for (i = 0; i < 0x200; i++) {
222 for (i = 0; i < (32768/8); i++) {
231 printf("%x: %x %x %x %x %x %x %x %x\n", i * 8,
232 c[0], c[1], c[2], c[3],
233 c[4], c[5], c[6], c[7]);
239 static unsigned char check_fpga(void)
242 do_spi(BB_AUTOINC | BB_REG_CTRL_BASE);
243 do_spi(0xff); /* pad */
244 c[0] = do_spi(0xff); /* Read data 0 : ID */
245 c[1] = do_spi(0xff); /* Read data 1 : Version */
248 printf("FPGA ID %x Version %d\n", c[0], c[1]);
249 if (c[0] != 0x42 && c[1] != 1) {
250 printf("Unsupported !\n");
254 /* Test CPU inteface latches */
256 do_spi(BB_WRITE | BB_AUTOINC | BB_REG_CPU_BASE);
266 do_spi(BB_AUTOINC | BB_REG_CPU_BASE);
276 if (c[0] != 0xde || c[1] != 0xad || c[2] != 0xbe ||
277 c[3] != 0xf0 || c[4] != 0x0d) {
278 printf("Latches test FAILED want:\n");
279 printf(" RW:1 U:1 L:1 ADDR: de ad be DATA: f0 0d\n");
284 printf("CPU interface latch test passed !\n");
289 /* Bits inverted from what goes into the SPI request */
290 #define SIM_CYCLE_READ 0x00
291 #define SIM_CYCLE_WRITE 0x01
292 #define SIM_CYCLE_UPPER 0x02
293 #define SIM_CYCLE_LOWER 0x04
294 #define SIM_CYCLE_WORD (SIM_CYCLE_UPPER | SIM_CYCLE_LOWER)
296 static unsigned short sim_bus_cycle(unsigned long addr,
302 /* Read value at 0x1020 */
304 do_spi(BB_WRITE | BB_AUTOINC | BB_REG_CPU_BASE);
305 do_spi((addr >> 16) & 0xff);
306 do_spi((addr >> 8) & 0xff);
307 do_spi((addr ) & 0xff);
308 do_spi((dat >> 8 ) & 0xff);
309 do_spi((dat ) & 0xff);
311 do_spi(0x04); /* ctrl: cycle */
314 /* Wait for stop state */
316 do_spi(BB_REG_CPU_BASE + 0x7);
320 while(!(stat & 0x08));
325 do_spi(BB_AUTOINC | BB_REG_CPU_BASE | 3);
335 static void dump_latches(void)
339 do_spi(BB_AUTOINC | BB_REG_CPU_BASE);
348 printf(" RW:%d U:%d L:%d ADDR: %x %x %x DATA: %x %x %s\n",
352 c[0], c[1], c[2], c[3], c[4],
353 SCSI_HSHAKE ? " [SCSI]" : "");
356 static void run_to(unsigned long addr)
362 do_spi(BB_WRITE | BB_AUTOINC | BB_REG_CPU_BASE | 8);
363 do_spi((addr >> 16) & 0xff);
364 do_spi((addr >> 8) & 0xff);
365 do_spi((addr ) & 0xff);
368 /* Start CPU with BP */
370 do_spi(BB_WRITE | BB_REG_CPU_BASE | 6);
371 do_spi(0x42); /* RUN + BKEN */
374 /* Wait for stop state */
376 do_spi(BB_REG_CPU_BASE + 0x7);
383 do_spi(BB_REG_CPU_BASE + 0x7);
387 } while(!(stat & 0x08));
391 static void step(unsigned short n)
395 for (i = 0; i < n; i++) {
398 do_spi(BB_WRITE | BB_REG_CPU_BASE | 6);
399 do_spi(0x82); /* RUN + STEP */
402 #if 0 /* Need in theory but CPU never fast enough */
403 /* Wait for stop state */
405 do_spi(BB_REG_CPU_BASE + 0x7);
409 while(!(stat & 0x08));
419 unsigned short v, v2;
423 printf("Initializing MMC...\n");
429 printf("Initializing FAT...\n");
435 printf("Configuring FPGA...\n");
437 if (!configure_fpga())
440 // printf("Checking FPGA...\n");
444 printf("Loading ROM file...\n");
445 if (!load_file("MIMIGMACROM", 0x200000))
448 printf("Loading Screenshot...\n");
449 if (!load_file("SCRNSHOTRAW", 0x1fa700))
453 printf("Opening SCSI disk image...\n");
459 do_spi(BB_WRITE | BB_REG_SCOPE_BASE);
463 /* Read ROM first words */
464 v = sim_bus_cycle(0, 0, SIM_CYCLE_READ | SIM_CYCLE_WORD);
465 v2 = sim_bus_cycle(2, 0, SIM_CYCLE_READ | SIM_CYCLE_WORD);
466 printf("Mem 0: %x %x\n", v, v2);
467 v = sim_bus_cycle(4, 0, SIM_CYCLE_READ | SIM_CYCLE_WORD);
468 v2 = sim_bus_cycle(6, 0, SIM_CYCLE_READ | SIM_CYCLE_WORD);
469 printf("Mem 4: %x %x\n", v, v2);
471 /* Read ROM las words */
472 v = sim_bus_cycle(0x41fff8, 0, SIM_CYCLE_READ | SIM_CYCLE_WORD);
473 v2 = sim_bus_cycle(0x41fffa, 0, SIM_CYCLE_READ | SIM_CYCLE_WORD);
474 printf("ROM end 0: %x %x\n", v, v2);
475 v = sim_bus_cycle(0x41fffc, 0, SIM_CYCLE_READ | SIM_CYCLE_WORD);
476 v2 = sim_bus_cycle(0x41fffe, 0, SIM_CYCLE_READ | SIM_CYCLE_WORD);
477 printf("ROM end 4: %x %x\n", v, v2);
482 do_spi(BB_WRITE | BB_REG_CTRL_BASE | 2);
488 unsigned char b,oldb,t;
491 do_spi(BB_REG_CTRL_BASE | 6);
498 if (b == oldb && t < 0xff)
507 for (i = 0; i < 512; i+=2)
508 printf("%x %x\n", secbuf[i], secbuf[i+1]);
515 // printf("Running to main()\n");
517 printf("Stepping...()\n");
523 for (i = 0; i < 1000; i++) {
533 printf("Running to exception \n");
541 printf("Running to P_mBootBeep...\n");
546 printf("Running to IWM init...\n");
551 printf("Running to P_ChecksumRomAndTestMemory...\n");
556 printf("Running to P_BootPart2 (fake hit)...\n");
561 printf("Running to P_BootPart2...\n");
569 /* Read video first words */
570 v = sim_bus_cycle(0x1fa700, 0, SIM_CYCLE_READ | SIM_CYCLE_WORD);
571 v2 = sim_bus_cycle(0x1fa702, 0, SIM_CYCLE_READ | SIM_CYCLE_WORD);
572 printf("Vid 0: %x %x\n", v, v2);
573 v = sim_bus_cycle(0x1fa704, 0, SIM_CYCLE_READ | SIM_CYCLE_WORD);
574 v2 = sim_bus_cycle(0x1fa706, 0, SIM_CYCLE_READ | SIM_CYCLE_WORD);
575 printf("Vid 4: %x %x\n", v, v2);
576 printf("Running to setting MemTop...\n");
587 v = sim_bus_cycle(0x108, 0, SIM_CYCLE_READ | SIM_CYCLE_WORD);
588 printf("Detected memory size: 0x%x0000 bytes\n", v);
589 printf("Running to L53 (CPUflag test)...\n");
592 for (i = 0; i < 50; i++) {
596 printf("Running to Bsr P5...\n");
599 printf("Running to call to _InitResources...\n");
604 printf("Running to P_mInitQueue...\n");
609 printf("Running to P_InitSCC...\n");
614 printf("Running to P_InitKeyboard...\n");
619 printf("Running to P_mInitIOMgr...\n");
627 printf("Running to P252...\n");
631 /* HWCfgFlags at 0xb22 bit 7 is SCSI */
632 v = sim_bus_cycle(0xb22, 0, SIM_CYCLE_READ | SIM_CYCLE_WORD);
633 printf("HWCfgFlags=%x\n", v >> 8);
634 v = sim_bus_cycle(0xb2e, 0, SIM_CYCLE_READ | SIM_CYCLE_WORD);
635 printf("SCSIDrvrs =%x\n", v >> 8);
637 printf("Running to SCSI driver jump...\n");
640 printf("Running to SCSI driver csum...\n");
646 printf("Running to after plot disk...\n");
649 v = sim_bus_cycle(0x30a, 0, SIM_CYCLE_READ | SIM_CYCLE_WORD);
650 v2 = sim_bus_cycle(0x30c, 0, SIM_CYCLE_READ | SIM_CYCLE_WORD);
651 printf("DrvQHdr.Head=%x %x\n", v, v2);
655 printf("Running to P_mInitIOMgr..x1...\n");
660 printf("Running to P_mInitIOMgr..x2...\n");
665 printf("Running to P_mInitIOMgr..x3...\n");
671 for (i = 0; i < 1000; i++) {
678 do_spi(BB_WRITE | BB_REG_CPU_BASE | 6);
684 /* This is VERY timing sensitive, the ROM selection
685 * timeout is very short and the fact that we run at
686 * twice the speed doesn't help.
687 * We could improve that by pre-setting the SPI to point
688 * to the SCSI lines register and just read from them,
689 * or we could have some of the selection logic moved to
692 * Better HACK: The FPGA could delay CPU read cycles
693 * from the bus status register when SEL
694 * is set by a significant amount in the
695 * FPGA thus allowing a lot more time for
696 * the selection process
703 printf("Running to E_Sony_Open...\n");
708 printf("Running to E_Sony_Open:17DFA (_VInstall)...\n");
713 printf("Running to E_Sony_Open:17E12 (bsr P721)...\n");
716 for (i = 0; i < 1000; i++) {
720 printf("Running to E_Sony_Open:17E16 (bsr P720)...\n");
723 for (i = 0; i < 100; i++) {
727 printf("Running to E_Sony_Open:17E24 (bsr P715)...\n");
734 for (i = 0; i < 1000; i++) {
738 printf("Running to L58...\n");
743 for (i = 0; i < 1000; i++) {
751 for (i = 0; i < 100; i++) {
754 do_spi(BB_WRITE | BB_REG_CPU_BASE | 6);
755 do_spi(0x01); /* RUN + STEP */
758 /* We shall wait for cycle to complete but we know
759 * how slow our SPI is ...
764 do_spi(BB_WRITE | BB_REG_CPU_BASE | 6);
765 do_spi(0x02); /* RUN + STEP */
771 do_spi(BB_WRITE | BB_REG_CPU_BASE | 6);
772 do_spi(0x01); /* RUN + STEP */
793 do_spi(BB_WRITE | BB_REG_SCOPE_BASE);
797 printf("Reading 0x1020 via SPI initiated read cycle: ");
798 v = sim_bus_cycle(0x1020, 0, SIM_CYCLE_READ | SIM_CYCLE_WORD);
801 /* Reading memory via RAM fifo */
803 do_spi(BB_WRITE | BB_AUTOINC | BB_REG_MEM_BASE);
804 do_spi(0x20); /* ROM base */
810 do_spi(BB_REG_MEM_BASE);
812 do_spi(0xff); /* one more dummy cycle with RAM fifo */
813 for (i = 0; i < 0x40; i++) {
814 printf(" %x", do_spi(0xff));
815 if ((i & 0xf) == 0xf)
824 do_spi(BB_WRITE | BB_REG_CPU_BASE | 6);
825 do_spi(0x02); /* RUN */