3 module sim_kbd(inout clk, inout dat);
4 `define CLK_HALF 5000 /* faster sim, should be more like 50000 */
19 $display("sim_kbd: Send %x", d);
21 p = ~(d[0] ^ d[1] ^ d[2] ^ d[3] ^
22 d[4] ^ d[5] ^ d[6] ^ d[7]);
23 sr = { 1'b1, p, d, 1'b0 };
28 while(i > 0 && ok) begin
30 $display("sim_kbd: Clock low, aborting send");
37 sr = { 1'b0, sr[10:1] };
62 while(i > 0 && ok) begin
64 $display("sim_kbd: Clock low, aborting receive");
70 sr = { dat != 0, sr[10:1] };
73 end // while (i > 0 && ok)
78 // $display("rx shift final: %b", sr);
84 $display("sim_kbd: Got %x ok=%b", d, ok);
91 assign clk = aclk ? 1'b0 : 1'bz;
92 assign dat = adat ? 1'b0 : 1'bz;
96 always@(clk, dat) begin
97 while (clk == 0) begin
106 $display("sim_kbd: LEDs set to %x\n", cmd);
108 if (cmd == 8'hed) begin
111 end else if (cmd == 8'hff) begin