#endif
static struct {
- int feature;
- unsigned mask;
+ uint32_t feature;
+ uint32_t mask;
bool use_edx; /* ecx will be used if false. */
} features[] = {
{ CF_MMX, 1 << 23, true },
{ CEF_XOP, 1 << 11, false }
};
-static bool has_feature(int feature, uint32_t ecx, uint32_t edx)
-{
- int i;
-
- for (i = 0; i < sizeof(features) / sizeof(features[0]); ++i) {
- if (features[i].feature == feature) {
- if (features[i].use_edx)
- return (edx & features[i].mask);
- else
- return (ecx & features[i].mask);
- }
- }
-
- return false;
-}
-
bool cpuid_is_supported(void)
{
int ret = 0;
+#if defined(__GNUC__) || defined(__clang__)
+ /* The following assembly code uses EAX as the return value,
+ * but we store the value of EAX into ret since GCC uses EAX
+ * as the return register for every C function. That's a double
+ * operation, but there's no other way to do this unless doing this
+ * function entirely in assembly.
+ *
+ * The following assembly code has been shamelessly stolen from:
+ * http://wiki.osdev.org/CPUID
+ * and converted to work with AT&T syntax.
+ *
+ * This check is to make sure that the compiler is actually compiling
+ * for 64-bit.
+ *
+ * The compiler can be 32-bit and the system 64-bit so the
+ * following would be true:
+ * #if defined(__x86_64) ...
+ */
+
+#if UINTPTR_MAX == 0xffffffffffffffff
+#define ASM_PUSHF "pushfq\n\t"
+#define ASM_POPF "popfq\n\t"
+#define ASM_PUSHEAX "pushq %%rax\n\t"
+#define ASM_POPEAX "popq %%rax\n\t"
+#define ASM_PUSHECX "pushq %%rcx\n\t"
+#elif UINTPTR_MAX == 0xffffffff
+#define ASM_PUSHF "pushfl\n\t"
+#define ASM_POPF "popfl\n\t"
+#define ASM_PUSHEAX "pushl %%eax\n\t"
+#define ASM_POPEAX "popl %%eax\n\t"
+#define ASM_PUSHECX "pushl %%ecx\n\t"
+#endif
asm volatile(
- "pushfl\n\t"
- "popl %%eax\n\t"
+ ASM_PUSHF
+ ASM_POPEAX
"movl %%eax, %%ecx\n\t"
"xorl $0x200000, %%eax\n\t"
- "pushl %%eax\n\t"
- "popfl\n\t"
-
- "pushfl\n\t"
- "popl %%eax\n\t"
+ ASM_PUSHEAX
+ ASM_POPF
+ ASM_PUSHF
+ ASM_POPEAX
"xorl %%ecx, %%eax\n\t"
"shrl $21, %%eax\n\t"
"andl $1, %%eax\n\t"
- "pushl %%ecx\n\t"
- "popfl\n\t"
-
+ ASM_PUSHECX
+ ASM_POPF
: "=a" (ret)
);
+#undef ASM_PUSHF
+#undef ASM_POPF
+#undef ASM_PUSHEAX
+#undef ASM_POPEAX
+#undef ASM_PUSHECX
+#elif defined _MSC_VER
+ __asm {
+ pushfd
+ pop eax
+ mov ecx, eax
+ xor eax, 0x200000
+ push eax
+ popfd
+
+ pushfd
+ pop eax
+ xor eax, ecx
+ shr eax, 0x21
+ and eax, 0x1
+ push ecx
+ popfd
+
+ mov eax, ret
+ };
+#endif
return !!ret;
}
bool cpuid_has_feature(int feature, bool extended)
{
- uint32_t eax, ebx, ecx, edx;
+ uint32_t eax, ebx, ecx, edx, i;
if (!extended)
___cpuid(CPU_PROCINFO_AND_FEATUREBITS, &eax, &ebx, &ecx, &edx);
else
___cpuid(CPU_EXTENDED_PROC_INFO_FEATURE_BITS, &eax, &ebx, &ecx, &edx);
- return has_feature(feature, ecx, edx);
+ for (i = 0; i < sizeof(features) / sizeof(features[0]); ++i) {
+ if (features[i].feature == feature) {
+ if (features[i].use_edx)
+ return (edx & features[i].mask);
+ else
+ return (ecx & features[i].mask);
+ }
+ }
+ return false;
}
-static const char *cpuids[] = {
+static const char *const cpuids[] = {
"Nooooooooone",
"AMDisbetter!",
"AuthenticAMD",
uint32_t i;
___cpuid(CPU_VENDORID, &i, &u.bufu32[0], &u.bufu32[2], &u.bufu32[1]);
- u.buf[12] = '\0';
-
for (i = 0; i < sizeof(cpuids) / sizeof(cpuids[0]); ++i) {
if (strncmp(cpuids[i], u.buf, 12) == 0) {
cputype = (cputype_t)i;
return cputype;
}
-const char *cpuid_get_cpu_type_string(const cputype_t cputype)
+bool cpuid_sprintf_cputype(const cputype_t cputype, char *buf)
{
- return cpuids[(int)cputype];
+ if (cputype == CT_NONE)
+ return false;
+
+ memcpy(buf, cpuids[(int)cputype], 12);
+ buf[12] = '\0';
+ return true;
}
uint32_t cpuid_highest_ext_func_supported(void)
static uint32_t highest;
if (!highest) {
+#if defined(__GNUC__) || defined(__clang__)
asm volatile(
"cpuid\n\t"
: "=a" (highest)
: "a" (CPU_HIGHEST_EXTENDED_FUNCTION_SUPPORTED)
);
+#elif defined _MSC_VER
+ __asm {
+ mov eax, CPU_HIGHEST_EXTENDED_FUNCTION_SUPPORTED
+ cpuid
+ mov highest, eax
+ };
+#endif
}
return highest;
return;
if (info == CPU_PROC_BRAND_STRING) {
- ___cpuid(CPU_PROC_BRAND_STRING, &buf[0], &buf[1], &buf[2], &buf[3]);
- ___cpuid(CPU_PROC_BRAND_STRING_INTERNAL0, &buf[4], &buf[5], &buf[6], &buf[7]);
- ___cpuid(CPU_PROC_BRAND_STRING_INTERNAL1, &buf[8], &buf[9], &buf[10], &buf[11]);
+ static char cached[48] = { 0 };
+ if (cached[0] == '\0') {
+ ___cpuid(CPU_PROC_BRAND_STRING, &buf[0], &buf[1], &buf[2], &buf[3]);
+ ___cpuid(CPU_PROC_BRAND_STRING_INTERNAL0, &buf[4], &buf[5], &buf[6], &buf[7]);
+ ___cpuid(CPU_PROC_BRAND_STRING_INTERNAL1, &buf[8], &buf[9], &buf[10], &buf[11]);
+
+ memcpy(cached, buf, sizeof cached);
+ } else
+ buf = (uint32_t *)cached;
+
return;
} else if (info == CPU_HIGHEST_EXTENDED_FUNCTION_SUPPORTED) {
*buf = cpuid_highest_ext_func_supported();
buf[1] = ecx;
break;
case CPU_L1_CACHE_AND_TLB_IDS:
+ buf[0] = eax;
+ buf[1] = ebx;
+ buf[2] = ecx;
+ buf[3] = edx;
break;
case CPU_EXTENDED_L2_CACHE_FEATURES:
- *buf = ecx;
+ buf[0] = ecx & 0xFF; /* Line size. */
+ buf[1] = (ecx >> 12) & 0xFF; /* Associativity. */
+ buf[2] = ecx >> 16; /* Cache size. */
break;
case CPU_ADV_POWER_MGT_INFO:
*buf = edx;
break;
case CPU_VIRT_PHYS_ADDR_SIZES:
- *buf = eax;
+ buf[0] = eax & 0xFF; /* physical. */
+ buf[1] = (eax >> 8) & 0xFF; /* virtual. */
break;
default:
*buf = 0xbaadf00d;
}
#endif
-
projects / ccan / blobdiff