pic/main.c

   1 #include <stdio.h>
   2 #include <ctype.h>
   3 #include <stdlib.h>
   4 #include <string.h>
   5
   6 #include "hardware.h"
   7 #include "mmc.h"
   8 #include "fat16.h"
   9 #include "scsi.h"
  10
  11 #define printf  printf_tiny
  12
  13 /* Sector buffer. Shared globally to save space on PIC
  14  *
  15  * XXX In this file to work around a missing bank select problem
  16  */
  17 unsigned char secbuf[512];
  18
  19 static char hex[] = {'0','1','2','3','4','5','6','7','8','9','a','b','c',
  20                      'd','e','f'};
  21
  22 /* Temp buffer used for tests */
  23 static unsigned char c[10];
  24
  25 static unsigned char load_file(char *name, unsigned long addr)
  26 {
  27         unsigned short t;
  28         unsigned short n;
  29         unsigned char *ptr = secbuf;
  30         long size;
  31
  32         size = fat_open(name);
  33         if (size < 0) {
  34                 printf("File %s not found !\n", name);
  35                 return false;
  36         }
  37         fat_file_seek(0);
  38
  39         spi_enable_fpga();
  40         do_spi(BB_WRITE | BB_AUTOINC | BB_REG_MEM_BASE);
  41         do_spi((addr >> 16) & 0xff);
  42         do_spi((addr >>  8) & 0xff);
  43         do_spi((addr      ) & 0xff);
  44         spi_disable_fpga();
  45
  46         t = 0;
  47         n = (size + 7) >> 3;
  48         do {
  49                 /* read sector if 512 (64*8) bytes done */
  50                 if ((t & 0x3f) == 0) {
  51                         if ((t>>9)&1)
  52                                 diskled_on();
  53                         else
  54                                 diskled_off();
  55                         putchar('*');
  56                         if (!fat_file_read()) {
  57                                 printf("Reading failed !\n");
  58                                 return false;
  59                         }
  60                         spi_enable_fpga();
  61                         do_spi(BB_WRITE | BB_REG_MEM_BASE | 3);
  62                         ptr = secbuf;
  63                 }
  64
  65                 /* send data in packets of 8 bytes */
  66                 do_spi(*(ptr++));
  67                 do_spi(*(ptr++));
  68                 do_spi(*(ptr++));
  69                 do_spi(*(ptr++));
  70                 do_spi(*(ptr++));
  71                 do_spi(*(ptr++));
  72                 do_spi(*(ptr++));
  73                 do_spi(*(ptr++));
  74                 t++;
  75
  76                 /* read next sector if 512 (64*8) bytes done */
  77                 if ((t & 0x3f) == 0) {
  78                         spi_disable_fpga();
  79                         fat_file_next_sector();
  80                 }
  81                 if ((t & 0x7ff) == 0)
  82                         putchar(10);
  83         } while (t < n);
  84         spi_disable_fpga();
  85
  86         putchar(10);
  87
  88         return true;
  89 }
  90
  91 static unsigned char configure_fpga(void)
  92 {
  93         unsigned short t;
  94         unsigned short n;
  95         unsigned char *ptr = secbuf;
  96         long size;
  97
  98         /* Reset FGPA configuration sequence */
  99         reset_fpga();
 100
 101         // now wait for INIT to go high
 102         t = 50000;
 103         while (!INIT_B) {
 104                 if (--t==0) {
 105                         printf("FPGA init is NOT high!\n");
 106                         return false;
 107                 }
 108         }
 109         if (DONE) {
 110                 printf("FPGA done is high before configuration!\n");
 111                 return false;
 112         }
 113
 114         /* Open bitstream file */
 115         size = fat_open("MIMIGMACBIN");
 116         if (size < 0) {
 117                 printf("No FPGA configuration file found!\n");
 118                 return false;
 119         }
 120         fat_file_seek(0);
 121
 122         /* Send all bytes to FPGA in loop */
 123         t = 0;
 124         n = size >> 3;
 125         do {
 126                 /* read sector if 512 (64*8) bytes done */
 127                 if ((t & 0x3f) == 0) {
 128                         if ((t>>9)&1)
 129                                 diskled_on();
 130                         else
 131                                 diskled_off();
 132                         putchar('*');
 133                         if (!fat_file_read()) {
 134                                 printf("Reading failed !\n");
 135                                 return false;
 136                         }
 137                         ptr = secbuf;
 138                 }
 139
 140                 /* send data in packets of 8 bytes */
 141                 shift_fpga(*(ptr++));
 142                 shift_fpga(*(ptr++));
 143                 shift_fpga(*(ptr++));
 144                 shift_fpga(*(ptr++));
 145                 shift_fpga(*(ptr++));
 146                 shift_fpga(*(ptr++));
 147                 shift_fpga(*(ptr++));
 148                 shift_fpga(*(ptr++));
 149                 t++;
 150
 151                 /* read next sector if 512 (64*8) bytes done */
 152                 if ((t & 0x3f) == 0)
 153                         fat_file_next_sector();
 154                 if ((t & 0x7ff) == 0)
 155                         putchar(10);
 156         } while (t < n);
 157
 158         shift_fpga(0xff);
 159         shift_fpga(0xff);
 160         shift_fpga(0xff);
 161         shift_fpga(0xff);
 162         shift_fpga(0xff);
 163         shift_fpga(0xff);
 164         shift_fpga(0xff);
 165         shift_fpga(0xff);
 166         shift_fpga(0xff);
 167         shift_fpga(0xff);
 168
 169         diskled_off();
 170
 171         /* check if DONE is high */
 172         if (DONE) {
 173                 shift_fpga(0xff);
 174                 shift_fpga(0xff);
 175                 shift_fpga(0xff);
 176                 shift_fpga(0xff);
 177                 shift_fpga(0xff);
 178                 shift_fpga(0xff);
 179                 shift_fpga(0xff);
 180                 shift_fpga(0xff);
 181                 shift_fpga(0xff);
 182                 shift_fpga(0xff);
 183                 putchar(10);
 184                 return true;
 185         }
 186
 187         printf("FPGA done is NOT high!\n");
 188         return false;
 189 }
 190
 191 static void print_latches(void)
 192 {
 193         printf("  RW:%d U:%d L:%d ADDR: %x %x %x DATA: %x %x\n",
 194                !!(c[5] & 0x01),
 195                !!(c[5] & 0x02),
 196                !!(c[5] & 0x04),
 197                c[0], c[1], c[2], c[3], c[4]);
 198 }
 199
 200 #if 1
 201 static void dump_scope(void)
 202 {
 203         unsigned short i;
 204
 205         /* Dump scope output */
 206         spi_enable_fpga();
 207         do_spi(BB_AUTOINC | BB_REG_SCOPE_BASE | 2);
 208         do_spi(0xff);
 209         c[0] = do_spi(0xff);
 210         c[1] = do_spi(0xff);
 211         printf("sample count: %x %x\n", c[0], c[1]);
 212         spi_disable_fpga();
 213         spi_enable_fpga();
 214         do_spi(BB_WRITE | BB_REG_SCOPE_BASE | 4);
 215         do_spi(0xff);
 216         spi_disable_fpga();
 217
 218         spi_enable_fpga();
 219         do_spi(BB_REG_SCOPE_BASE | 4);
 220         do_spi(0xff);
 221         //      for (i = 0; i < 0x200; i++) {
 222         for (i = 0; i < (32768/8); i++) {
 223                 c[0] = do_spi(0xff);
 224                 c[1] = do_spi(0xff);
 225                 c[2] = do_spi(0xff);
 226                 c[3] = do_spi(0xff);
 227                 c[4] = do_spi(0xff);
 228                 c[5] = do_spi(0xff);
 229                 c[6] = do_spi(0xff);
 230                 c[7] = do_spi(0xff);
 231                 printf("%x: %x %x %x %x %x %x %x %x\n", i * 8,
 232                        c[0], c[1], c[2], c[3],
 233                        c[4], c[5], c[6], c[7]);
 234         }
 235         spi_disable_fpga();
 236 }
 237 #endif
 238
 239 static unsigned char check_fpga(void)
 240 {
 241         spi_enable_fpga();
 242         do_spi(BB_AUTOINC | BB_REG_CTRL_BASE);
 243         do_spi(0xff);   /* pad */
 244         c[0] = do_spi(0xff);    /* Read data 0 : ID */
 245         c[1] = do_spi(0xff);    /* Read data 1 : Version */
 246         spi_disable_fpga();
 247
 248         printf("FPGA ID %x Version %d\n", c[0], c[1]);
 249         if (c[0] != 0x42 && c[1] != 1) {
 250                 printf("Unsupported !\n");
 251                 return false;
 252         }
 253
 254         /* Test CPU inteface latches */
 255         spi_enable_fpga();
 256         do_spi(BB_WRITE | BB_AUTOINC | BB_REG_CPU_BASE);
 257         do_spi(0xde);
 258         do_spi(0xad);
 259         do_spi(0xbf);
 260         do_spi(0xf0);
 261         do_spi(0x0d);
 262         do_spi(0xff);
 263         spi_disable_fpga();
 264
 265         spi_enable_fpga();
 266         do_spi(BB_AUTOINC | BB_REG_CPU_BASE);
 267         do_spi(0xff);
 268         c[0] = do_spi(0xff);
 269         c[1] = do_spi(0xff);
 270         c[2] = do_spi(0xff);
 271         c[3] = do_spi(0xff);
 272         c[4] = do_spi(0xff);
 273         c[5] = do_spi(0xff);
 274         spi_disable_fpga();
 275
 276         if (c[0] != 0xde || c[1] != 0xad || c[2] != 0xbe ||
 277             c[3] != 0xf0 || c[4] != 0x0d) {
 278                 printf("Latches test FAILED want:\n");
 279                 printf("  RW:1 U:1 L:1 ADDR: de ad be DATA: f0 0d\n");
 280                 printf("Got:\n");
 281                 print_latches();
 282                 return false;
 283         }
 284         printf("CPU interface latch test passed !\n");
 285
 286         return true;
 287 }
 288
 289 /* Bits inverted from what goes into the SPI request */
 290 #define SIM_CYCLE_READ  0x00
 291 #define SIM_CYCLE_WRITE 0x01
 292 #define SIM_CYCLE_UPPER 0x02
 293 #define SIM_CYCLE_LOWER 0x04
 294 #define SIM_CYCLE_WORD  (SIM_CYCLE_UPPER | SIM_CYCLE_LOWER)
 295
 296 static unsigned short sim_bus_cycle(unsigned long addr,
 297                                     unsigned short dat,
 298                                     unsigned char flags)
 299 {
 300         unsigned char stat;
 301
 302         /* Read value at 0x1020 */
 303         spi_enable_fpga();
 304         do_spi(BB_WRITE | BB_AUTOINC | BB_REG_CPU_BASE);
 305         do_spi((addr >> 16) & 0xff);
 306         do_spi((addr >>  8) & 0xff);
 307         do_spi((addr      ) & 0xff);
 308         do_spi((dat  >> 8 ) & 0xff);
 309         do_spi((dat       ) & 0xff);
 310         do_spi(~flags);
 311         do_spi(0x04); /* ctrl: cycle */
 312         spi_disable_fpga();
 313
 314         /* Wait for stop state */
 315         spi_enable_fpga();
 316         do_spi(BB_REG_CPU_BASE + 0x7);
 317         do_spi(0xff);
 318         do
 319                 stat = do_spi(0xff);
 320         while(!(stat & 0x08));
 321         spi_disable_fpga();
 322
 323         /* Read latches */
 324         spi_enable_fpga();
 325         do_spi(BB_AUTOINC | BB_REG_CPU_BASE | 3);
 326         do_spi(0xff);
 327         dat  = do_spi(0xff);
 328         dat  <<= 8;
 329         dat  |= do_spi(0xff);
 330         spi_disable_fpga();
 331
 332         return dat ;
 333 }
 334
 335 static void dump_latches(void)
 336 {
 337         /* Read latches */
 338         spi_enable_fpga();
 339         do_spi(BB_AUTOINC | BB_REG_CPU_BASE);
 340         do_spi(0xff);
 341         c[0] = do_spi(0xff);
 342         c[1] = do_spi(0xff);
 343         c[2] = do_spi(0xff);
 344         c[3] = do_spi(0xff);
 345         c[4] = do_spi(0xff);
 346         c[5] = do_spi(0xff);
 347         spi_disable_fpga();
 348         printf("  RW:%d U:%d L:%d ADDR: %x %x %x DATA: %x %x %s\n",
 349                !!(c[5] & 0x01),
 350                !!(c[5] & 0x02),
 351                !!(c[5] & 0x04),
 352                c[0], c[1], c[2], c[3], c[4],
 353                SCSI_HSHAKE ? " [SCSI]" : "");
 354 }
 355
 356 static void run_to(unsigned long addr)
 357 {
 358         unsigned char stat;
 359
 360         /* Set breakpoint */
 361         spi_enable_fpga();
 362         do_spi(BB_WRITE | BB_AUTOINC | BB_REG_CPU_BASE | 8);
 363         do_spi((addr >> 16) & 0xff);
 364         do_spi((addr >>  8) & 0xff);
 365         do_spi((addr      ) & 0xff);
 366         spi_disable_fpga();
 367
 368         /* Start CPU with BP */
 369         spi_enable_fpga();
 370         do_spi(BB_WRITE | BB_REG_CPU_BASE | 6);
 371         do_spi(0x42); /* RUN + BKEN */
 372         spi_disable_fpga();
 373
 374         /* Wait for stop state */
 375         spi_enable_fpga();
 376         do_spi(BB_REG_CPU_BASE + 0x7);
 377         do_spi(0xff);
 378         do {
 379                 if (SCSI_HSHAKE) {
 380                         spi_disable_fpga();
 381                         do_scsi();
 382                         spi_enable_fpga();
 383                         do_spi(BB_REG_CPU_BASE + 0x7);
 384                         do_spi(0xff);
 385                 }
 386                 stat = do_spi(0xff);
 387         } while(!(stat & 0x08));
 388         spi_disable_fpga();
 389 }
 390
 391 static void step(unsigned short n)
 392 {
 393         unsigned short i;
 394
 395         for (i = 0; i < n; i++) {
 396                 /* Step CPU */
 397                 spi_enable_fpga();
 398                 do_spi(BB_WRITE | BB_REG_CPU_BASE | 6);
 399                 do_spi(0x82); /* RUN + STEP */
 400                 spi_disable_fpga();
 401
 402 #if 0 /* Need in theory but CPU never fast enough */
 403                 /* Wait for stop state */
 404                 spi_enable_fpga();
 405                 do_spi(BB_REG_CPU_BASE + 0x7);
 406                 do_spi(0xff);
 407                 do
 408                         stat = do_spi(0xff);
 409                 while(!(stat & 0x08));
 410                 spi_disable_fpga();
 411 #endif
 412         }
 413 }
 414
 415 void main(void)
 416 {
 417         unsigned char rc;
 418         unsigned short i;
 419         unsigned short v, v2;
 420
 421         hardware_init();
 422
 423         printf("Initializing MMC...\n");
 424
 425         rc = mmc_init();
 426         if (!rc)
 427                 return;
 428
 429         printf("Initializing FAT...\n");
 430
 431         rc = fat_init();
 432         if (!rc)
 433                 return;
 434
 435         printf("Configuring FPGA...\n");
 436
 437         if (!configure_fpga())
 438                 return;
 439
 440         //      printf("Checking FPGA...\n");
 441         if (!check_fpga())
 442                 return;
 443
 444         printf("Loading ROM file...\n");
 445         if (!load_file("MIMIGMACROM", 0x200000))
 446                 return;
 447 #if 0
 448         printf("Loading Screenshot...\n");
 449         if (!load_file("SCRNSHOTRAW", 0x1fa700))
 450                 return;
 451 #endif
 452
 453         printf("Opening SCSI disk image...\n");
 454         scsi_open();
 455
 456 #if 0
 457         /* Start scope */
 458         spi_enable_fpga();
 459         do_spi(BB_WRITE | BB_REG_SCOPE_BASE);
 460         do_spi(0x02);
 461         spi_disable_fpga();
 462
 463         /* Read ROM first words */
 464         v = sim_bus_cycle(0, 0, SIM_CYCLE_READ | SIM_CYCLE_WORD);
 465         v2 = sim_bus_cycle(2, 0, SIM_CYCLE_READ | SIM_CYCLE_WORD);
 466         printf("Mem 0: %x %x\n", v, v2);
 467         v = sim_bus_cycle(4, 0, SIM_CYCLE_READ | SIM_CYCLE_WORD);
 468         v2 = sim_bus_cycle(6, 0, SIM_CYCLE_READ | SIM_CYCLE_WORD);
 469         printf("Mem 4: %x %x\n", v, v2);
 470
 471         /* Read ROM las words */
 472         v = sim_bus_cycle(0x41fff8, 0, SIM_CYCLE_READ | SIM_CYCLE_WORD);
 473         v2 = sim_bus_cycle(0x41fffa, 0, SIM_CYCLE_READ | SIM_CYCLE_WORD);
 474         printf("ROM end 0: %x %x\n", v, v2);
 475         v = sim_bus_cycle(0x41fffc, 0, SIM_CYCLE_READ | SIM_CYCLE_WORD);
 476         v2 = sim_bus_cycle(0x41fffe, 0, SIM_CYCLE_READ | SIM_CYCLE_WORD);
 477         printf("ROM end 4: %x %x\n", v, v2);
 478 #endif
 479
 480         /* Un-reset CPU */
 481         spi_enable_fpga();
 482         do_spi(BB_WRITE | BB_REG_CTRL_BASE | 2);
 483         do_spi(0x01);
 484         spi_disable_fpga();
 485
 486 #if 0
 487         {
 488                 unsigned char b,oldb,t;
 489
 490                 spi_enable_fpga();
 491                 do_spi(BB_REG_CTRL_BASE | 6);
 492                 do_spi(0xff);
 493                 oldb = 0;
 494                 t = 0, i = 0;
 495                 while (i < 512) {
 496                         oldb = b;
 497                         b = do_spi(0xff);
 498                         if (b == oldb && t < 0xff)
 499                             t++;
 500                         else {
 501                                 secbuf[i++] = b;
 502                                 secbuf[i++] = t;
 503                                 t = 0;
 504                         }
 505                 }
 506                 spi_disable_fpga();
 507                 for (i = 0; i < 512; i+=2)
 508                         printf("%x %x\n", secbuf[i], secbuf[i+1]);
 509         }
 510 #endif
 511
 512 #if 0
 513
 514
 515         //      printf("Running to main()\n");
 516         //      run_to(0x4010c8);
 517         printf("Stepping...()\n");
 518         dump_latches();
 519         step(1);
 520         dump_latches();
 521         step(1);
 522
 523         for (i = 0; i < 1000; i++) {
 524                 step(1);
 525                 dump_latches();
 526         }
 527
 528         for (;;)
 529                 ;
 530 #endif
 531 #if 0
 532         for (;;) {
 533                 printf("Running to exception \n");
 534                 run_to(0x401336);
 535                 dump_latches();
 536                 step(1);
 537         }
 538 #endif
 539
 540 #if 0
 541         printf("Running to P_mBootBeep...\n");
 542         run_to(0x40028a);
 543         dump_latches();
 544         step(1);
 545         dump_latches();
 546         printf("Running to IWM init...\n");
 547         run_to(0x4000fc);
 548         dump_latches();
 549         step(1);
 550         dump_latches();
 551         printf("Running to P_ChecksumRomAndTestMemory...\n");
 552         run_to(0x400d76);
 553         dump_latches();
 554         step(1);
 555         dump_latches();
 556         printf("Running to P_BootPart2 (fake hit)...\n");
 557         run_to(0x400352);
 558         dump_latches();
 559         step(1);
 560         dump_latches();
 561         printf("Running to P_BootPart2...\n");
 562         run_to(0x400352);
 563         dump_latches();
 564         step(1);
 565         dump_latches();
 566 #endif
 567
 568 #if 0
 569         /* Read video first words */
 570         v = sim_bus_cycle(0x1fa700, 0, SIM_CYCLE_READ | SIM_CYCLE_WORD);
 571         v2 = sim_bus_cycle(0x1fa702, 0, SIM_CYCLE_READ | SIM_CYCLE_WORD);
 572         printf("Vid 0: %x %x\n", v, v2);
 573         v = sim_bus_cycle(0x1fa704, 0, SIM_CYCLE_READ | SIM_CYCLE_WORD);
 574         v2 = sim_bus_cycle(0x1fa706, 0, SIM_CYCLE_READ | SIM_CYCLE_WORD);
 575         printf("Vid 4: %x %x\n", v, v2);
 576         printf("Running to setting MemTop...\n");
 577         run_to(0x40037e);
 578         dump_latches();
 579         step(1);
 580         dump_latches();
 581         step(1);
 582         dump_latches();
 583         step(1);
 584         dump_latches();
 585         step(1);
 586         dump_latches();
 587         v = sim_bus_cycle(0x108, 0, SIM_CYCLE_READ | SIM_CYCLE_WORD);
 588         printf("Detected memory size: 0x%x0000 bytes\n", v);
 589         printf("Running to L53 (CPUflag test)...\n");
 590         run_to(0x400584);
 591         dump_latches();
 592         for (i = 0; i < 50; i++) {
 593                 step(1);
 594                 dump_latches();
 595         }
 596         printf("Running to Bsr P5...\n");
 597         run_to(0x4005fa);
 598         dump_latches();
 599         printf("Running to call to _InitResources...\n");
 600         run_to(0x400600);
 601         dump_latches();
 602         step(1);
 603         dump_latches();
 604         printf("Running to P_mInitQueue...\n");
 605         run_to(0x401a38);
 606         dump_latches();
 607         step(1);
 608         dump_latches();
 609         printf("Running to P_InitSCC...\n");
 610         run_to(0x40082c);
 611         dump_latches();
 612         step(1);
 613         dump_latches();
 614         printf("Running to P_InitKeyboard...\n");
 615         run_to(0x402568);
 616         dump_latches();
 617         step(1);
 618         dump_latches();
 619         printf("Running to P_mInitIOMgr...\n");
 620         run_to(0x40087c);
 621         dump_latches();
 622         step(1);
 623         dump_latches();
 624 #endif
 625 #if 0
 626
 627         printf("Running to P252...\n");
 628         run_to(0x407d40);
 629         dump_latches();
 630
 631         /* HWCfgFlags at 0xb22 bit 7 is SCSI */
 632         v = sim_bus_cycle(0xb22, 0, SIM_CYCLE_READ | SIM_CYCLE_WORD);
 633         printf("HWCfgFlags=%x\n", v >> 8);
 634         v = sim_bus_cycle(0xb2e, 0, SIM_CYCLE_READ | SIM_CYCLE_WORD);
 635         printf("SCSIDrvrs =%x\n", v >> 8);
 636
 637         printf("Running to SCSI driver jump...\n");
 638         run_to(0x407dc4);
 639         dump_latches();
 640         printf("Running to SCSI driver csum...\n");
 641         run_to(0x1d36);
 642         dump_latches();
 643 #endif
 644
 645 #if 0
 646         printf("Running to after plot disk...\n");
 647         run_to(0x4006e4);
 648         dump_latches();
 649         v = sim_bus_cycle(0x30a, 0, SIM_CYCLE_READ | SIM_CYCLE_WORD);
 650         v2 = sim_bus_cycle(0x30c, 0, SIM_CYCLE_READ | SIM_CYCLE_WORD);
 651         printf("DrvQHdr.Head=%x %x\n", v, v2);
 652 #endif
 653
 654 #if 0
 655         printf("Running to P_mInitIOMgr..x1...\n");
 656         run_to(0x40089c);
 657         dump_latches();
 658         step(1);
 659         dump_latches();
 660         printf("Running to P_mInitIOMgr..x2...\n");
 661         run_to(0x4008a6);
 662         dump_latches();
 663         step(1);
 664         dump_latches();
 665         printf("Running to P_mInitIOMgr..x3...\n");
 666         run_to(0x4008ac);
 667         dump_latches();
 668 #endif
 669
 670 #if 0
 671         for (i = 0; i < 1000; i++) {
 672                 step(1);
 673                 dump_latches();
 674         }
 675 #endif
 676         /* Run CPU */
 677         spi_enable_fpga();
 678         do_spi(BB_WRITE | BB_REG_CPU_BASE | 6);
 679         do_spi(0x02);
 680         spi_disable_fpga();
 681
 682         i = 0;
 683         for (;;) {
 684                 /* This is VERY timing sensitive, the ROM selection
 685                  * timeout is very short and the fact that we run at
 686                  * twice the speed doesn't help.
 687                  * We could improve that by pre-setting the SPI to point
 688                  * to the SCSI lines register and just read from them,
 689                  * or we could have some of the selection logic moved to
 690                  * the FPGA
 691                  *
 692                  * Better HACK: The FPGA could delay CPU read cycles
 693                  *              from the bus status register when SEL
 694                  *              is set by a significant amount in the
 695                  *              FPGA thus allowing a lot more time for
 696                  *              the selection process
 697                  */
 698                 if (SCSI_HSHAKE)
 699                         do_scsi();
 700         }
 701
 702 #if 0
 703         printf("Running to E_Sony_Open...\n");
 704         run_to(0x417d9e);
 705         dump_latches();
 706         step(1);
 707         dump_latches();
 708         printf("Running to E_Sony_Open:17DFA (_VInstall)...\n");
 709         run_to(0x417dfa);
 710         dump_latches();
 711         step(1);
 712         dump_latches();
 713         printf("Running to E_Sony_Open:17E12 (bsr P721)...\n");
 714         run_to(0x417e12);
 715         dump_latches();
 716         for (i = 0; i < 1000; i++) {
 717                 step(1);
 718                 dump_latches();
 719         }
 720         printf("Running to E_Sony_Open:17E16 (bsr P720)...\n");
 721         run_to(0x417e12);
 722         dump_latches();
 723         for (i = 0; i < 100; i++) {
 724                 step(1);
 725                 dump_latches();
 726         }
 727         printf("Running to E_Sony_Open:17E24 (bsr P715)...\n");
 728         run_to(0x417e12);
 729         dump_latches();
 730         step(1);
 731         dump_latches();
 732         step(1);
 733         dump_latches();
 734         for (i = 0; i < 1000; i++) {
 735                 step(1);
 736                 dump_latches();
 737         }
 738         printf("Running to L58...\n");
 739         run_to(0x400692);
 740         dump_latches();
 741         step(1);
 742         dump_latches();
 743         for (i = 0; i < 1000; i++) {
 744                 step(1);
 745                 dump_latches();
 746         }
 747 #endif
 748
 749
 750 #if 0
 751         for (i = 0; i < 100; i++) {
 752                 wait_timer(100);
 753                 spi_enable_fpga();
 754                 do_spi(BB_WRITE | BB_REG_CPU_BASE | 6);
 755                 do_spi(0x01); /* RUN + STEP */
 756                 spi_disable_fpga();
 757
 758                 /* We shall wait for cycle to complete but we know
 759                  * how slow our SPI is ...
 760                  */
 761                 dump_latches();
 762
 763                 spi_enable_fpga();
 764                 do_spi(BB_WRITE | BB_REG_CPU_BASE | 6);
 765                 do_spi(0x02); /* RUN + STEP */
 766                 spi_disable_fpga();
 767         }
 768
 769         /* Stop CPU */
 770         spi_enable_fpga();
 771         do_spi(BB_WRITE | BB_REG_CPU_BASE | 6);
 772         do_spi(0x01); /* RUN + STEP */
 773         spi_disable_fpga();
 774 #endif
 775
 776 #if 0
 777         step(10000);
 778         step(10000);
 779         step(10000);
 780         step(10000);
 781         step(10000);
 782         step(10000);
 783         step(10000);
 784         step(10000);
 785         step(10000);
 786         step(10000);
 787         step(10000);
 788 #endif
 789
 790 #if 0
 791         /* Stop scope */
 792         spi_enable_fpga();
 793         do_spi(BB_WRITE | BB_REG_SCOPE_BASE);
 794         do_spi(0x00);
 795         spi_disable_fpga();
 796
 797         printf("Reading 0x1020 via SPI initiated read cycle: ");
 798         v = sim_bus_cycle(0x1020, 0, SIM_CYCLE_READ | SIM_CYCLE_WORD);
 799         printf("%x\n", v);
 800
 801         /* Reading memory via RAM fifo */
 802         spi_enable_fpga();
 803         do_spi(BB_WRITE | BB_AUTOINC | BB_REG_MEM_BASE);
 804         do_spi(0x20); /* ROM base */
 805         do_spi(0x10);
 806         do_spi(0x00);
 807         spi_disable_fpga();
 808
 809         spi_enable_fpga();
 810         do_spi(BB_REG_MEM_BASE);
 811         do_spi(0xff);
 812         do_spi(0xff); /* one more dummy cycle with RAM fifo */
 813         for (i = 0; i < 0x40; i++) {
 814                 printf(" %x", do_spi(0xff));
 815                 if ((i & 0xf) == 0xf)
 816                         printf("\n");
 817         }
 818         printf("\n");
 819 #endif
 820
 821 #if 0
 822         /* Start CPU */
 823         spi_enable_fpga();
 824         do_spi(BB_WRITE | BB_REG_CPU_BASE | 6);
 825         do_spi(0x02); /* RUN */
 826         spi_disable_fpga();
 827 #endif
 828
 829 #if 0
 830         for (;;)
 831                 ;
 832 #endif
 833 }