3 /* SPI to backbus interface for minimigmac
5 * This layers on top of the spi_slave module. It provides a protocol
6 * which allows to read and write from of 8-bit wide, 6 addr bit bus
7 * which is connected to various modules in the system.
9 * The basic SPI protocol starts with one byte received by the FPGA,
10 * which is has the format <RW:1> <AI:1> <ADDR:6>
12 * RW : Read (0) / Write (1)
14 * ADDR : Register address
16 * For writes, all subsequent bytes are directly relevant. For reads,
17 * the next byte after the read command shall be ignored, then subsequent
20 * The backbus side protocol is:
22 * - Writes: at clock with strobe high and wr high, data and address
23 * are stable and shall be latched.
24 * - Reads : at clock with strobe high and wr low, address stable,
25 * we latch data immediately.
34 /* SPI signals (through to the SPI slave core) */
40 /* Backbus interface */
41 output reg [5:0] bb_addr,
42 output [7:0] bb_wdata,
52 /* Protocol internals */
60 /* Instanciate SPI slave interface */
61 spi_slave spi0(.sysclk(sysclk),
73 always@(posedge sysclk or posedge reset) begin
77 /* Latch read data at read strobe */
78 if (bb_strobe && !bb_wr)
83 /* One state machine to rule them all coz I'm lazy */
84 always@(posedge sysclk or posedge reset) begin
88 /* Command byte. Establish addr, wr and set strobe on read */
89 if (spi_rx && spi_cmd) begin
90 bb_addr <= bb_wdata[5:0];
91 delayed_ainc <= bb_wdata[6];
92 ainc <= bb_wdata[7] ? 0 : bb_wdata[6];
94 bb_strobe <= ~bb_wdata[7];
95 end else if (spi_rx) begin
96 /* Subsequent bytes */
99 bb_addr <= bb_addr + 1;