4 * Generate clocks for simulation
8 * - sysclk16 at 16.6666Mhz (60ns)
9 * - sysclk33 at 33.3333Mhz (30ns)
12 module clockgen(input mclk, /* ignored */
24 #30 sysclk16 = ~sysclk16;
27 #15 sysclk33 = ~sysclk33;
34 /* The xilinx OFDDRCPE IO module is simulated here for iverilog */
48 assign Q = c == 0 ? D0 : D1;
50 always@(posedge C0 or posedge C1 or posedge CLR or posedge PRE) begin