5 /* Interface between FPGA and other siumulated components */
9 wire [23:1] cpu_address;
21 wire [19:1] ram_address;
56 wire mclk; /* Note: Ignored in sim */
70 /* Unused CPU output pins */
74 /* Instanciate 4 SRAM modules */
75 sim_sram512x16 ram0(.addr(ram_address),
83 sim_sram512x16 ram1(.addr(ram_address),
91 sim_sram512x16 ram2(.addr(ram_address),
99 sim_sram512x16 ram3(.addr(ram_address),
107 /* Instanciate CPU. Lotsa stuff not wired on Minimig */
108 m68k cpu0(.clk(cpu_clk),
127 defparam cpu.turbo = 1;
128 // defparam cpu.log_flags = 0;
129 // defparam cpu.log_flags = 'hff;
131 /* Instanciate the FPGA */
132 minimigmac minimigmac0(.cpu_data(cpu_data),
133 .cpu_address(cpu_address),
139 ._cpu_dtack(_cpu_dtack),
140 ._cpu_reset(_cpu_reset),
143 .ram_address(ram_address),
172 .scsi_hshake(scsi_hshake),
178 sim_pic pic0(.sdo(sdi),
182 .scsi_hshake(scsi_hshake),
185 sim_mouse mouse0(.clk(msclk), .dat(msdat));
186 sim_kbd kbd0(.clk(kbdclk), .dat(kbddat));
192 $dumpfile("sim_bench.vcd");
193 $dumpvars(0,minimigmac0);
202 $display("Loading ROM...");
203 rom_file = $fopenr("rom.bin");
204 rom_size = $fread(ram2.mem, rom_file, 0);
206 $display("Loaded 0x%h bytes", rom_size);
207 $display("ram[841]=%h", ram2.mem['h841]);
208 $display("Disabling mem test");
209 ram0.mem['h2a2/2] = 'h0040;
210 ram0.mem['h2a4/2] = 'h0000;
211 $display("Disabling boot beep & clr screen etc...");
212 ram2.mem['hf4/2] = 'h4e71;
213 ram2.mem['hf6/2] = 'h4e71;
214 ram2.mem['hea/2] = 'h4e71;
215 ram2.mem['hec/2] = 'h4e71;
216 ram2.mem['h34/2] = 'h4e71;
217 ram2.mem['h36/2] = 'h4e71;
218 ram2.mem['h38/2] = 'h4e71;
219 ram2.mem['h3a/2] = 'h4e71;
220 ram2.mem['h3c/2] = 'h4e71;
221 ram2.mem['h3e/2] = 'h4e71;
222 ram2.mem['h40/2] = 'h4e71;
223 /* checksum & test memory replaced with
224 * movea.l #memsize, a5 and beq->bra
226 ram2.mem['h12a/2] = 'h2a7c;
227 ram2.mem['h12c/2] = 'h0020;
228 ram2.mem['h12e/2] = 'h0000;
229 ram2.mem['h130/2] = 'h4e71;
230 ram2.mem['h132/2] = 'h6000;
231 ram0.mem['h108/2] = 'h0020; /* memtop */
232 ram0.mem['h10a/2] = 'h0000;