2 `define CTRL_REG_FPGA_ID 0
3 `define CTRL_REG_FPGA_VERSION 1
5 /* WO: Global control register */
6 `define CTRL_REG_GCTRL 2
7 `define GCTRL_CPU_UNRESET_BIT 0
9 /* RO: PS2 Mouse Debug */
10 `define CTRL_REG_PS2M_DBG0 3
11 `define CTRL_REG_PS2M_DBG1 4
13 /* RO: PS2 Kbd Debug */
14 `define CTRL_REG_PS2K_DBG0 5
15 `define CTRL_REG_PS2K_DBG1 6
22 /* Backbus interface */
25 output [7:0] bb_rdata,
30 input [15:0] ps2m_dbg,
31 input [15:0] ps2k_dbg,
33 /* Generated control signals */
36 /* Latched registers */
39 assign cpu_reset = ~gctrl[`GCTRL_CPU_UNRESET_BIT];
41 assign bb_rdata = (bb_addr[2:0] == `CTRL_REG_FPGA_ID) ? 8'h42 :
42 (bb_addr[2:0] == `CTRL_REG_FPGA_VERSION) ? 8'h01 :
43 (bb_addr[2:0] == `CTRL_REG_GCTRL) ? gctrl :
44 (bb_addr[2:0] == `CTRL_REG_PS2M_DBG0) ? ps2m_dbg[15:8] :
45 (bb_addr[2:0] == `CTRL_REG_PS2M_DBG1) ? ps2m_dbg[7:0] :
46 (bb_addr[2:0] == `CTRL_REG_PS2K_DBG0) ? ps2k_dbg[15:8] :
47 (bb_addr[2:0] == `CTRL_REG_PS2K_DBG1) ? ps2k_dbg[7:0] :
50 /* Register interface */
51 always@(posedge sysclk or posedge reset) begin
55 if (bb_strobe && bb_wr) begin