1 default,all: sim_bench.vcd
3 SRC := sim_bench.v sim_clocks.v sim_sram.v sim_pic.v sim_mouse.v sim_kbd.v
4 SRC += m68k.v cpu_intf.v addr_decode.v
5 SRC += mem_intf.v via6522.v iwm.v ncr5380.v scc.v
6 SRC += spi_backbus.v spi_slave.v scope.v ctrl.v
7 SRC += video.v rtc.v ps2.v ps2_mouse.v ps2_kbd.v
11 iverilog -g2 -Wall -tvvp -D__IVERILOG__ -o $@ $^
13 sim_bench.vcd: sim_bench.vvp m68k_vpi.vpi
14 vvp -M. -mm68k_vpi sim_bench.vvp
17 gtkwave ./sim_bench.vcd