`timescale 1ns / 100ps /* * Generate clocks for simulation * * We generate: * * - sysclk16 at 16.6666Mhz (60ns) * - sysclk33 at 33.3333Mhz (30ns) * */ module clockgen(input mclk, /* ignored */ output reg sysclk16, output reg sysclk33, output reg pixclk); initial begin sysclk16 = 0; sysclk33 = 0; pixclk = 0; end always begin #30 sysclk16 = ~sysclk16; end always begin #15 sysclk33 = ~sysclk33; end always begin #20 pixclk = ~pixclk; end endmodule /* The xilinx OFDDRCPE IO module is simulated here for iverilog */ module OFDDRCPE ( output Q, input C0, input C1, input CE, input CLR, input D0, input D1, input PRE ); reg c = 0; assign Q = c == 0 ? D0 : D1; always@(posedge C0 or posedge C1 or posedge CLR or posedge PRE) begin if (CLR) c = 0; else if (PRE) c = 1; else if (CE) begin if (C0) c = 0; else if (C1) c = 1; end end endmodule