`timescale 1ns / 100ps

module main();

	/* Interface between FPGA and other siumulated components */

	/* m68k interface */
	wire [15:0] 	cpu_data;
	wire [23:1] 	cpu_address;
	wire [2:0] 	_cpu_ipl;
	wire 		_cpu_as;
	wire 		_cpu_uds;
	wire 		_cpu_lds;
	wire 		cpu_r_w;
	wire 		_cpu_dtack;
	wire 		_cpu_reset;
	wire 		cpu_clk;

	/* SRAM interface */
	wire [15:0] 	ram_data;
	wire [19:1] 	ram_address;
	wire [3:0] 	_ram_ce;	
	wire 		_ram_bhe;
	wire 		_ram_ble;
	wire 		_ram_we;
	wire 		_ram_oe;	

	/* RS232 pins */
	wire 		rxd;
	wire 		txd;
	wire 		cts;
	wire 		rts;

	/* Joystick ports */
	wire [5:0] 	_joy1;
	wire [5:0] 	_joy2;

	/* PS2 ports */
	wire 		msdat;
	wire 		msclk;
	wire 		kbddat;
	wire 		kbdclk;

	/* Video pins */
	wire 		_hsync;
	wire 		_vsync;
	wire [3:0] 	red;
	wire [3:0] 	green;
	wire [3:0] 	blue;

	/* Audio pins */
	wire 		left;
	wire 		right;

	/* System pins */
	wire 		mclk; /* Note: Ignored in sim */
	wire 		pwrled;
	wire 		init_b;
	wire 		_15khz;
	wire 		gpio;
 	wire  		scsi_hshake;
 	wire		nmi;
	
	/* SPI pins */
	wire 		_spi_cs;	
	wire 		sdi;
	wire 		sdo;
	wire 		sck;

	/* Unused CPU output pins */
	wire [2:0] 	cpu_fc;
	wire		_cpu_bg;
		
	/* Instanciate 4 SRAM modules */
	sim_sram512x16 ram0(.addr(ram_address),
			    .data(ram_data),
			    ._cs(_ram_ce[0]),
			    ._oe(_ram_oe),
			    ._we(_ram_we),
			    ._ub(_ram_bhe),
			    ._lb(_ram_ble));
	
	sim_sram512x16 ram1(.addr(ram_address),
			    .data(ram_data),
			    ._cs(_ram_ce[1]),
			    ._oe(_ram_oe),
			    ._we(_ram_we),
			    ._ub(_ram_bhe),
			    ._lb(_ram_ble));
	
	sim_sram512x16 ram2(.addr(ram_address),
			    .data(ram_data),
			    ._cs(_ram_ce[2]),
			    ._oe(_ram_oe),
			    ._we(_ram_we),
			    ._ub(_ram_bhe),
			    ._lb(_ram_ble));
	
	sim_sram512x16 ram3(.addr(ram_address),
			    .data(ram_data),
			    ._cs(_ram_ce[3]),
			    ._oe(_ram_oe),
			    ._we(_ram_we),
			    ._ub(_ram_bhe),
			    ._lb(_ram_ble));
	
	/* Instanciate CPU. Lotsa stuff not wired on Minimig */
	m68k cpu0(.clk(cpu_clk),
		 .fc(cpu_fc),
		 .a(cpu_address),
		 ._as(_cpu_as),
		 ._uds(_cpu_uds),
		 ._lds(_cpu_lds),
		 .r_w(cpu_r_w),
		 ._dtack(_cpu_dtack),
		 .d(cpu_data),
		 ._ipl(_cpu_ipl),
		 ._avec(1'b1),
		 ._br(1'b1),
		 ._bg(_cpu_bg),
		 ._berr(1'b1),
		 ._reset(_cpu_reset),
		 ._halt(1'b1));

	pullup(_cpu_reset);	
	
      defparam cpu.turbo = 1;
//	defparam cpu.log_flags = 0;
//	defparam cpu.log_flags = 'hff;

	/* Instanciate the FPGA */
	minimigmac minimigmac0(.cpu_data(cpu_data),
			       .cpu_address(cpu_address),
			       ._cpu_ipl(_cpu_ipl),
			       ._cpu_uds(_cpu_uds),
			       ._cpu_lds(_cpu_lds),
			       ._cpu_as(_cpu_as),
			       .cpu_r_w(cpu_r_w),
			       ._cpu_dtack(_cpu_dtack),
			       ._cpu_reset(_cpu_reset),
			       .cpu_clk(cpu_clk),
			       .ram_data(ram_data),
			       .ram_address(ram_address),
			       ._ram_ce(_ram_ce),
			       ._ram_bhe(_ram_bhe),
			       ._ram_ble(_ram_ble),
			       ._ram_we(_ram_we),
			       ._ram_oe(_ram_oe),
			       .rxd(rxd),
			       .txd(txd),
			       .cts(cts),
			       .rts(rts),
			       ._joy1(_joy1),
			       ._joy2(_joy2),
			       .msdat(msdat),
			       .msclk(msclk),
			       .kbddat(kbddat),
			       .kbdclk(kbdclk),
			       ._hsync(_hsync),
			       ._vsync(_vsync),
			       .red(red),
			       .green(green),
			       .blue(blue),
			       .left(left),
			       .right(right),
			       .mclk(mclk),
			       .pwrled(pwrled),
			       .init_b(init_b),
			       ._15khz(_15khz),
			       .gpio(gpio),
			       .nmi(nmi),
			       .scsi_hshake(scsi_hshake),
			       ._spi_cs(_spi_cs),
			       .sdi(sdi),
			       .sdo(sdo),
			       .sck(sck));

	sim_pic pic0(.sdo(sdi),
		     .sdi(sdo),
		     .sck(sck),
		     ._spi_cs(_spi_cs),
		     .scsi_hshake(scsi_hshake),
		     .nmi(nmi));

	sim_mouse mouse0(.clk(msclk), .dat(msdat));
	sim_kbd kbd0(.clk(kbdclk), .dat(kbddat));

	integer rom_file;
	integer rom_size;

	initial begin
                $dumpfile("sim_bench.vcd");
                $dumpvars(0,minimigmac0);
                $dumpvars(0,ram0);
                $dumpvars(0,ram1);
                $dumpvars(0,ram2);
                $dumpvars(0,ram3);
                $dumpvars(0,pic0);
                $dumpvars(0,cpu0);
                $dumpvars(0,mouse0);

		$display("Loading ROM...");
		rom_file = $fopenr("rom.bin");
		rom_size = $fread(ram2.mem, rom_file, 0);
		$fclose(rom_file);
		$display("Loaded 0x%h bytes", rom_size);
		$display("ram[841]=%h", ram2.mem['h841]);
		$display("Disabling mem test");
		ram0.mem['h2a2/2] = 'h0040;
		ram0.mem['h2a4/2] = 'h0000;
		$display("Disabling boot beep & clr screen etc...");
		ram2.mem['hf4/2] = 'h4e71;
		ram2.mem['hf6/2] = 'h4e71;
		ram2.mem['hea/2] = 'h4e71;		
		ram2.mem['hec/2] = 'h4e71;
		ram2.mem['h34/2] = 'h4e71;
		ram2.mem['h36/2] = 'h4e71;
		ram2.mem['h38/2] = 'h4e71;
		ram2.mem['h3a/2] = 'h4e71;	
		ram2.mem['h3c/2] = 'h4e71;
		ram2.mem['h3e/2] = 'h4e71;	
		ram2.mem['h40/2] = 'h4e71;
		/* checksum & test memory replaced with
		 * movea.l #memsize, a5 and beq->bra
		 */
		ram2.mem['h12a/2] = 'h2a7c;		
		ram2.mem['h12c/2] = 'h0020;
		ram2.mem['h12e/2] = 'h0000;
		ram2.mem['h130/2] = 'h4e71;
		ram2.mem['h132/2] = 'h6000;
		ram0.mem['h108/2] = 'h0020; /* memtop */
		ram0.mem['h10a/2] = 'h0000;
		#50000000;
		$finish;
	end
endmodule