/* RW: ID registers */
`define CTRL_REG_FPGA_ID	0
`define CTRL_REG_FPGA_VERSION	1

/* WO: Global control register */
`define CTRL_REG_GCTRL		2
`define     GCTRL_CPU_UNRESET_BIT	0

/* RO: PS2 Mouse Debug */
`define CTRL_REG_PS2M_DBG0	3
`define CTRL_REG_PS2M_DBG1	4

/* RO: PS2 Kbd Debug */
`define CTRL_REG_PS2K_DBG0	5
`define CTRL_REG_PS2K_DBG1	6

module ctrl
(
	input				sysclk,
 	input				reset,

	/* Backbus interface */
	input [5:0] 			bb_addr,
	input [7:0] 			bb_wdata,
	output [7:0] 			bb_rdata,
	input				bb_strobe,
	input				bb_wr,

 	/* Debug stuff */
 	input [15:0]			ps2m_dbg,
 	input [15:0]			ps2k_dbg,

	/* Generated control signals */
 	output 				cpu_reset
);
	/* Latched registers */
	reg [7:0] 			gctrl;

	assign cpu_reset = ~gctrl[`GCTRL_CPU_UNRESET_BIT];

	assign bb_rdata = (bb_addr[2:0] == `CTRL_REG_FPGA_ID) ? 8'h42 :
			  (bb_addr[2:0] == `CTRL_REG_FPGA_VERSION) ? 8'h01 :
			  (bb_addr[2:0] == `CTRL_REG_GCTRL) ? gctrl :
			  (bb_addr[2:0] == `CTRL_REG_PS2M_DBG0) ? ps2m_dbg[15:8] :
			  (bb_addr[2:0] == `CTRL_REG_PS2M_DBG1) ? ps2m_dbg[7:0] :
			  (bb_addr[2:0] == `CTRL_REG_PS2K_DBG0) ? ps2k_dbg[15:8] :
			  (bb_addr[2:0] == `CTRL_REG_PS2K_DBG1) ? ps2k_dbg[7:0] :
			  0;

	/* Register interface */
	always@(posedge sysclk or posedge reset) begin
		if (reset) begin
			gctrl <= 0;
		end else begin
			if (bb_strobe && bb_wr) begin
				case(bb_addr[2:0])
					`CTRL_REG_GCTRL:
					  gctrl <= bb_wdata;
				endcase
			end
		end
	end
endmodule