`timescale 1ns / 100ps

/* Mac Plus address space
 *
 * - 000000  RAM (or ROM when overlay enabled)
 * 
 * - 400000  ROM
 * 	WARNING: The ROM does a fun test to decide whether SCSI is availble
 *               or not (MacPlus vs. Mac512KE ?). It basically tests if
 * 		 (0x420000) == (0x440000) and if it -is- then it assumes
 *               SCSI is -not- there. So we must not "replicate" the ROM
 *               in our address decoding. 
 * 
 * 
 * - 580000  SCSI
 *   580drn
 *      ||\
 *      |\ \ b0000=Rd b0001=Wr
 *      | \- reg (b0000...b0111)
 *      \----b00d0 where d=dack
 *  (repeated to 5fffff)
 *
 * - 600000  RAM copy when overlay enabled (max 2M)
 *           (should we just always decode that ?)
 * - 800000
 * 
 * - 9FFFF7  ?? SCC Reset ? (*)
 * 
 * - 9FFFF8  SCC Rd (LDS=read UDS=write)
 * - BFFFF9  SCC Wr
 *     +0 Ch B control
 *     +2 Ch A control
 *     +4 Ch B data
 *     +6 Ch B data
 * 
 * - DFE1FF  IWM
 *
 * 	+ 0000 = DFE1FF = ph0L   : CA0 = 0
 *	+ 0200 = DFE3FF = ph0H   : CA0 = 1
 *	+ 0400 = DFE5FF = ph1L   : CA1 = 0
 *	+ 0600 = DFE7FF = ph1H   : CA1 = 1
 *	+ 0800 = DFE9FF = ph2L   : CA2 = 0
 *	+ 0A00 = DFEBFF = ph2H   : CA2 = 1
 *	+ 0C00 = DFEDFF = ph3L   : LSTRB = 0
 *	+ 0E00 = DFEFFF = ph3H   : LSTRB = 1
 *      + 1000 = DFF1FF = mtrOff : ENABLE = 0
 *      + 1200 = DFF3FF = mtrOn  : ENABLE = 1
 *      + 1400 = DFF5FF = intDrv : SELECT = 0
 *      + 1600 = DFF7FF = extDrv : SELECT = 1
 *	+ 1800 = DFF9FF = q6L    : Q6 = 0
 *	+ 1A00 = DFFBFF = q6H    : Q6 = 1
 *	+ 1C00 = DFFDFF = q7L    : Q7 = 0
 *	+ 1E00 = DFFFFF = q7H    : Q7 = 1
 * 
 * - EFE1FE  VIA
 *   Ex[xxxr][rrr1]xx - rrrr is RS3..RS0
 * 
 *    Port A (reg 0x1 or 0xf)
 *     0x07  O Sound volume
 *     0x08  O 1=Main snd buf 0=Alt snd buf
 *     0x10  O 1=ROM overlay (pullup, so set at boot)
 *     0x20  O Disk SEL line
 *     0x40  O 1=Main video 0=Alt video
 *     0x80  I SCC WReq
 * 
 *    Port B (reg 0x0)
 *     0x01 IO RTC data
 *     0x02  O RTC clock
 *     0x04  O RTC enable
 *     0x08  I Mouse switch
 *     0x10  I Mouse X2
 *     0x20  I Mouse Y2
 *     0x40  I HBlank
 *     0x80  O 1=Sound disable 0=Enable
 * 
 * - F00000  PhaseRead (according FDiasm) (*)
 *
 * - F80000  Expansion ROM
 * 
 * - FFFFF?  Autovector interrupt sim (we only check for top 6 bits 1)
 *
 * I am not certain how that "phase" setting works. Essentially we just
 * return all 1's and the ROM seems happy enough. What happens is that
 * very early at boot, the ROM does:
 * 
 *     movem.w (0xf0000000), d0-d2
 * 
 * Loading thus the 3 half words from f0000000, f0000002 and f0000004
 * into d0, d1 and d2 respectively.
 * 
 * It then does a byte read of 9ffff7 which I believe resets the SCC.
 * 
 * It then extracts the low order bit of the 3 reads above, adds them
 * up, substracts one, and check if the results is 0 or -1 (ie check
 * if at least 2 of those reads had bit 0 set).
 * 
 * If yes, it then does a "phase adjust" by reading a word from 9ffff8,
 * and that's about it.
 */

/*
 * Combinational address decoder, returns a chip select for each
 * device. Handles the special casing of the ROM overlay and major
 * devices.
 * 
 * Returns cs_nack for a non-existing address region
 * 
 * We are quite lax with decoding to save logic, I haven't verified
 * how "precise" a real macplus is but I haven't been anal at beeing
 * as lax as possible neither...
 */
module addr_decode(addr, req, rom_ovl,
		   cs_ram, cs_rom, cs_scsi, cs_scc, cs_iwm, cs_via,
		   cs_ivec, cs_nack);
	input [23:1]	addr;
	input		req;	
	input 		rom_ovl;
	output reg	cs_ram;
	output reg	cs_rom;
	output reg	cs_scsi;
	output reg	cs_scc;
	output reg	cs_iwm;
	output reg	cs_via;
	output reg	cs_ivec;
 	output reg	cs_nack;

	always@(addr or req or rom_ovl) begin
		cs_ram = 0;
		cs_rom = 0;
		cs_scsi = 0;
		cs_scc = 0;
		cs_iwm = 0;
		cs_via = 0;
		cs_ivec = 0;		
		cs_nack = 0;

		casez({req,addr[23:18],rom_ovl})
			8'b100????0: cs_ram = 1;
			8'b100????1: cs_rom = 1;
			8'b1010000?: cs_rom = 1;
			8'b101011??: cs_scsi = 1;
			8'b1011????: cs_ram = 1; /* only ovl=1 ? */
			8'b110?1???: cs_scc = 1;
			8'b11101???: cs_iwm = 1;
			8'b11110???: cs_via = 1;
			8'b1111111?: cs_ivec =1;				
			default: cs_nack = req;
		endcase
	end
endmodule