From 27f2cb1942b6391d3081016260e0d29b0ffa74f6 Mon Sep 17 00:00:00 2001 From: Jeremy Kerr Date: Sun, 19 Nov 2006 23:08:45 +1100 Subject: [PATCH 1/1] Minor changes to register class Signed-off-by: Jeremy Kerr --- bitfield | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/bitfield b/bitfield index 32a0405..3651677 100644 --- a/bitfield +++ b/bitfield @@ -77,13 +77,15 @@ class register: self.width = width self.fields = [] - def add_field(self, field,): + def add_field(self, field): self.fields.append(field) def decode(self, value, ignore_zero): field_width = (self.width + 3) / 4 name_width = max(map(lambda f: len(f.name), self.fields)) + str = "0x%0*lx [%d]\n" % (field_width, value, value) + for field in self.fields: v = field.mask(self.width, value); if ignore_zero and v == 0: -- 2.39.2