From 21c80144b197f4ecc2a4199a72b9ba271f56d171 Mon Sep 17 00:00:00 2001
From: Jeremy Kerr <jk@ozlabs.org>
Date: Tue, 29 Jul 2008 13:22:00 +1000
Subject: [PATCH] Add &mask syntax

This change adds a new syntax for bitfield definitions:

field: &0xff00 top 16-bits

This allows a mask (rather than mask << shift) value to be specified.

Signed-off-by: Jeremy Kerr <jk@ozlabs.org>
---
 ChangeLog | 1 +
 bitfield  | 8 ++++++++
 2 files changed, 9 insertions(+)

diff --git a/ChangeLog b/ChangeLog
index 0d9feae..094262f 100644
--- a/ChangeLog
+++ b/ChangeLog
@@ -1,4 +1,5 @@
 version ??
+	* Add support for &mask syntax
 	* Allow alternate (bit 0 is lsb) bit numbering scheme
 	* Add support for mask<<shift field definitions
 	* Add configuration for a few radeon registers
diff --git a/bitfield b/bitfield
index 467bf6b..3851c4c 100644
--- a/bitfield
+++ b/bitfield
@@ -57,6 +57,10 @@ class bitfield:
 				bits.insert(0, width - i - 1 - shift)
 		return bits
 
+	@staticmethod
+	def mask_to_bits(width, mask):
+		return bitfield.mask_and_shift_to_bits(width, mask, 0)
+
 	@staticmethod
 	def parse_bitfield(line, reg):
 		a = line.split(None, 1)
@@ -78,6 +82,10 @@ class bitfield:
 					s.split('<<'))
 				bits.extend(bitfield.mask_and_shift_to_bits( \
 					reg.width, mask, shift))
+			elif s.startswith('&'):
+				mask = int(s[1:], 0)
+				bits.extend(bitfield.mask_to_bits(reg.width, \
+							mask))
 			else:
 				bits.append(reg.bit_number(int(s)))
 
-- 
2.39.2