From: Jeremy Kerr <jk@ozlabs.org>
Date: Sun, 19 Nov 2006 12:08:45 +0000 (+1100)
Subject: Minor changes to register class
X-Git-Url: https://git.ozlabs.org/?p=bitfield;a=commitdiff_plain;h=27f2cb1942b6391d3081016260e0d29b0ffa74f6;ds=sidebyside

Minor changes to register class

Signed-off-by: Jeremy Kerr <jk@ozlabs.org>
---

diff --git a/bitfield b/bitfield
index 32a0405..3651677 100644
--- a/bitfield
+++ b/bitfield
@@ -77,13 +77,15 @@ class register:
 		self.width = width
 		self.fields = []
 
-	def add_field(self, field,):
+	def add_field(self, field):
 		self.fields.append(field)
 
 	def decode(self, value, ignore_zero):
 		field_width = (self.width + 3) / 4
 		name_width = max(map(lambda f: len(f.name), self.fields))
+
 		str = "0x%0*lx [%d]\n" % (field_width, value, value)
+
 		for field in self.fields:
 			v = field.mask(self.width, value);
 			if ignore_zero and v == 0: