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(parent: d1717c4) | patch
Add order: config option to define the bit ordering of register definitions
authorJeremy Kerr <jk@ozlabs.org>
Wed, 22 Nov 2006 02:30:47 +0000 (13:30 +1100)
committerJeremy Kerr <jk@ozlabs.org>
Thu, 12 Nov 2009 23:58:45 +0000 (10:58 +1100)
commitd9bbf176f2c7bc78746e2817d481b2bcbb8ab699
tree528ce123405419761749278072dbb2f572fbd7f5tree | snapshot (tar.gz zip)
parentd1717c40dd6fe30fdeb5f26064f57af71d3079afcommit | diff
Add order: config option to define the bit ordering of register definitions

Register definitions can now be entered with numbering schemes other than
the current default of bit 0 being the MSB. Valid values of the order:
configuration directive are: bit-0-is-lsb, bit-0-is-msb or ibm.

Signed-off-by: Jeremy Kerr <jk@ozlabs.org>
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tool to decode bitfield values