X-Git-Url: https://git.ozlabs.org/?p=bitfield;a=blobdiff_plain;f=conf%2Fpowerpc.conf;h=c9fc1ab0aa90d128e13112743ecb9ff89ca9882a;hp=1303d93c27c37af07dcb3fdce734dec0334e7cf2;hb=025475cf89a6a8b4253e5f23e5d8c78f0ffd0762;hpb=219644343e2219a5c13cebb462fb4159e1e4ca5c;ds=sidebyside

diff --git a/conf/powerpc.conf b/conf/powerpc.conf
index 1303d93..c9fc1ab 100644
--- a/conf/powerpc.conf
+++ b/conf/powerpc.conf
@@ -2,24 +2,23 @@
 ;
 ; Contributors:
 ;  Michael Neuling <mikey@neuling.org>
+;  Jeremy Kerr <jk@ozlabs.org>
 ;
 ; Taken from:
 ;    PowerPC® Microprocessor Family:
 ;    The Programming Environments Manual for 32 and 64-bit Microprocessors
-;    Version 2.3
+;    Version 2.03
 ;    http://www.power.org/resources/downloads/PowerISA_203.Public.pdf
 ;
 
-; Section 2.3.1 Machine State Register (MSR)
+; Section 3.2.1 Machine State Register (MSR)
 [MSR_64]
 name: PowerPC Machine State Register
 field:  0 64-bit mode (SF)
 value:		0 32-bit mode
 value:		1 64-bit mode
-field:  2 Exception 64-bit mode
 field:  3 Hypervisor State (HV)
-field: 45 Power Management Enable (POW)
-field: 47 Little-Endian Exception Mode (ILE)
+field: 38 Vector Available (VEC)
 field: 48 External Interrupt Enable (EE)
 field: 49 Problem State (PR)
 value:		0 privileged state
@@ -67,3 +66,74 @@ field: 56   Class (C)
 value:		0 big-endian
 value:		1 little-endian
 
+
+; The PowerPC Architecture:
+; A Specification For A New Family Of RISC Processors
+; Book III PowerPC Operating Environment Architecture
+
+; Section 2.2.3 Machine State Register (MSR)
+[MSR_32]
+name: PowerPC Machine State Register
+width: 32
+field: 13 Power Management Enable (POW)
+field: 15 Little-Endian Exception Mode (ILE)
+field: 16 External Interrupt Enable (EE)
+field: 17 Problem State (PR)
+value:		0 privileged state
+value:		1 problem state
+field: 18 Floating-Point Available (FP)
+field: 19 Machine Check Interrupt Enable (ME)
+field: 20,23 Floating-Point Exception Mode (FE)
+value:          0 ignore exceptions
+value:          1 imprecise nonrecoverable
+value:          2 imprecise recoverable
+value:          3 precise
+field: 21 Single-Step Trace Enable (SE)
+field: 22 Branch Trace Enable (BE)
+field: 26 Instruction Relocate (IR)
+field: 27 Data Relocate (DR)
+field: 30 Recoverable Interrupt (RI)
+field: 31 Little-Endian Mode (LE)
+value:		0 big-endian
+value:		1 little-endian
+
+; POWER ISA(tm) Book III-S
+; Section 5.7.6.1 Page Table
+
+[PTE_V]
+name: Page Table Entry, Dword 0
+field: 0:1 Segment Size (B)
+value:          0 256MB
+value:          1 1TB
+value:          2 reserved
+value:          3 reserved
+field: 2:56 Abbreviated Virtual Page Number (AVPN)
+field: 57:60 Software bits (SW)
+field: 61 Virtual page size (L)
+value:          0 4KB
+value:          1 large page
+field: 62 Hash function identifier (H)
+field: 63 Valid (V)
+
+[PTE_R]
+name: Page Table Entry, Dword 1
+field: 2:43 Appreviated Real Page Number (ARPN)
+field: 44:51 Large page size selector (LP)
+field: 54 Address Compare bit (AC)
+field: 55 Reference bit (R)
+field: 56 Change bit (C)
+field: 57 Storage control bit (W)
+field: 58 Storage control bit (I)
+field: 59 Storage control bit (M)
+field: 60 Storage control bit (G)
+field: 61 No-execute page (N)
+field: 62:63 Page protection bits (PP)
+value:          0 Key=0 read/write K=1 no access
+value:          1 Key=0 read/write K=1 read only
+value:          2 Key=0 read/write K=1 read/write
+value:          3 Key=0 read only  K=1 read only
+
+[SDR1]
+name: PowerPC Storage Description register
+field:  2:45 Real address of Page Table (HTABORG)
+field: 59:63 Encoded size of Page Table (HTABSIZE)