X-Git-Url: https://git.ozlabs.org/?p=bitfield;a=blobdiff_plain;f=bitfield;h=a35fd206b3484ae9d33779013b42edea42a29cf0;hp=d6d0f8bea1166b176a22cc11a7dae368165dca89;hb=6af82b47cb07a95e48d0a578b9e18141950a4ed3;hpb=a21c53b16fcc102e086df2eeedd11e843e5909fc

diff --git a/bitfield b/bitfield
index d6d0f8b..a35fd20 100644
--- a/bitfield
+++ b/bitfield
@@ -1,4 +1,4 @@
-#!/usr/bin/python2.4
+#!/usr/bin/env python
 #
 # Utility to decode register values
 # Copyright (c) 2006 Jeremy Kerr <jk@ozlabs.org>
@@ -29,15 +29,20 @@ class bitfield:
 		return len(self.bits)
 
 	def add_value(self, value, description):
-		self.values[int(value)] = description
+		self.values[int(value, 0)] = description
 
-	def mask(self, reg_width, value):
+	def mask(self, reg, value):
 		ret = 0
 		out_len = len(self.bits)
-		for out_bit in range(0, out_len):
-			in_bit = self.bits[out_bit]
+
+		if reg.bit_order == reg.bit_0_is_msb:
+			bit_pairs = zip(self.bits, range(0, out_len))
+		else:
+			bit_pairs = zip(self.bits, range(out_len - 1, -1, -1))
+
+		for (in_bit, out_bit) in bit_pairs:
 			# shift this bit down to the LSB (and mask the rest)
-			i = (value >> (reg_width - in_bit - 1)) & 1
+			i = (value >> (reg.width - in_bit - 1)) & 1
 			# shift back to the output position in the field
 			i <<= out_len - out_bit - 1
 			ret |= i
@@ -54,9 +59,13 @@ class bitfield:
 		val = mask << shift
 		for i in range(0, width):
 			if mask & (1 << i):
-				bits.append(width - i - 1 - shift)
+				bits.insert(0, width - i - 1 - shift)
 		return bits
 
+	@staticmethod
+	def mask_to_bits(width, mask):
+		return bitfield.mask_and_shift_to_bits(width, mask, 0)
+
 	@staticmethod
 	def parse_bitfield(line, reg):
 		a = line.split(None, 1)
@@ -70,14 +79,16 @@ class bitfield:
 				(start, end) = map( \
 					lambda s: reg.bit_number(int(s)),
 					s.split(':'))
-				start = reg.bit_number(int(start))
-				end = reg.bit_number(int(end))
-				bits.extend(range(start, end + 1, 1))
+				bits.extend(range(start, end - 1, -1))
 			elif '<<' in s:
 				(mask, shift) = map(lambda s: int(s.strip()),
 					s.split('<<'))
 				bits.extend(bitfield.mask_and_shift_to_bits( \
 					reg.width, mask, shift))
+			elif s.startswith('&'):
+				mask = int(s[1:], 0)
+				bits.extend(bitfield.mask_to_bits(reg.width, \
+							mask))
 			else:
 				bits.append(reg.bit_number(int(s)))
 
@@ -114,7 +125,7 @@ class register:
 		str = "0x%0*lx [%d]\n" % (field_width, value, value)
 
 		for field in self.fields:
-			v = field.mask(self.width, value);
+			v = field.mask(self, value);
 			if ignore_zero and v == 0:
 				continue
 			desc = field.value(v)
@@ -128,7 +139,7 @@ class register:
 
 	def bit_number(self, number):
 		if self.bit_order == self.bit_0_is_lsb:
-			number = self.width - 1 - number
+			number = self.width - number - 1
 		return number
 
 def list_regs(regs):