X-Git-Url: https://git.ozlabs.org/?p=bitfield;a=blobdiff_plain;f=bitfield;h=a35fd206b3484ae9d33779013b42edea42a29cf0;hp=5ade7af4fac6e03832e4d294cc7bae86aa14e284;hb=6af82b47cb07a95e48d0a578b9e18141950a4ed3;hpb=d9bbf176f2c7bc78746e2817d481b2bcbb8ab699

diff --git a/bitfield b/bitfield
index 5ade7af..a35fd20 100644
--- a/bitfield
+++ b/bitfield
@@ -1,4 +1,4 @@
-#!/usr/bin/python2.4
+#!/usr/bin/env python
 #
 # Utility to decode register values
 # Copyright (c) 2006 Jeremy Kerr <jk@ozlabs.org>
@@ -29,15 +29,20 @@ class bitfield:
 		return len(self.bits)
 
 	def add_value(self, value, description):
-		self.values[int(value)] = description
+		self.values[int(value, 0)] = description
 
-	def mask(self, reg_width, value):
+	def mask(self, reg, value):
 		ret = 0
 		out_len = len(self.bits)
-		for out_bit in range(0, out_len):
-			in_bit = self.bits[out_bit]
+
+		if reg.bit_order == reg.bit_0_is_msb:
+			bit_pairs = zip(self.bits, range(0, out_len))
+		else:
+			bit_pairs = zip(self.bits, range(out_len - 1, -1, -1))
+
+		for (in_bit, out_bit) in bit_pairs:
 			# shift this bit down to the LSB (and mask the rest)
-			i = (value >> (reg_width - in_bit - 1)) & 1
+			i = (value >> (reg.width - in_bit - 1)) & 1
 			# shift back to the output position in the field
 			i <<= out_len - out_bit - 1
 			ret |= i
@@ -48,6 +53,19 @@ class bitfield:
 			return self.values[value]
 		return None
 
+	@staticmethod
+	def mask_and_shift_to_bits(width, mask, shift):
+		bits = []
+		val = mask << shift
+		for i in range(0, width):
+			if mask & (1 << i):
+				bits.insert(0, width - i - 1 - shift)
+		return bits
+
+	@staticmethod
+	def mask_to_bits(width, mask):
+		return bitfield.mask_and_shift_to_bits(width, mask, 0)
+
 	@staticmethod
 	def parse_bitfield(line, reg):
 		a = line.split(None, 1)
@@ -58,15 +76,26 @@ class bitfield:
 		bits = []
 		for s in range_str.split(','):
 			if ':' in s:
-				(start, end) = s.split(':')
-				start = reg.bit_number(int(start))
-				end = reg.bit_number(int(end))
-				bits.extend(range(start, end + 1, 1))
+				(start, end) = map( \
+					lambda s: reg.bit_number(int(s)),
+					s.split(':'))
+				bits.extend(range(start, end - 1, -1))
+			elif '<<' in s:
+				(mask, shift) = map(lambda s: int(s.strip()),
+					s.split('<<'))
+				bits.extend(bitfield.mask_and_shift_to_bits( \
+					reg.width, mask, shift))
+			elif s.startswith('&'):
+				mask = int(s[1:], 0)
+				bits.extend(bitfield.mask_to_bits(reg.width, \
+							mask))
 			else:
 				bits.append(reg.bit_number(int(s)))
- 
+
 		return bitfield(bits, name)
 
+
+
 	@staticmethod
 	def parse_value(line):
 		a = line.split(None, 1)
@@ -96,7 +125,7 @@ class register:
 		str = "0x%0*lx [%d]\n" % (field_width, value, value)
 
 		for field in self.fields:
-			v = field.mask(self.width, value);
+			v = field.mask(self, value);
 			if ignore_zero and v == 0:
 				continue
 			desc = field.value(v)
@@ -107,10 +136,10 @@ class register:
 				str += "%*s: 0x%x\n" \
 					% (name_width, field.name, v)
 		return str
-	
+
 	def bit_number(self, number):
 		if self.bit_order == self.bit_0_is_lsb:
-			number = self.width - 1 - number
+			number = self.width - number - 1
 		return number
 
 def list_regs(regs):
@@ -178,12 +207,14 @@ def parse_config(bnf, regs, file):
 						+ "fields in %s") % id)
 
 				order_str = t[1].strip().lower()
+				order_str = order_str.replace(' ', '-')
+
 				if order_str not in order_map.keys():
 					raise ConfigurationError(file,
 						"Invalid bit order %s in %s" % \
 						(order_str, id))
 				reg.bit_order = order_map[order_str]
-				
+
 			elif t[0] == 'alias':
 				alias_id = t[1].strip()
 
@@ -329,7 +360,7 @@ def main():
 		value_iter = args.__iter__()
 	else:
 		value_iter = iter(sys.stdin.readline, '')
-		
+
 	try:
 		for value in value_iter:
 			decode_value(reg, value.strip(), options)