Added 32-bit MSR to powerpc definitions

[bitfield] / conf / powerpc.conf

diff --git a/conf/powerpc.conf b/conf/powerpc.conf
index 1303d93c27c37af07dcb3fdce734dec0334e7cf2..8e124cc869c7ebe0f414140ad2c0093930e86241 100644 (file)
--- a/conf/powerpc.conf
+++ b/conf/powerpc.conf
@@ -2,6 +2,7 @@
 ;
 ; Contributors:
 ;  Michael Neuling <mikey@neuling.org>
 ;
 ; Contributors:
 ;  Michael Neuling <mikey@neuling.org>

+;  Jeremy Kerr <jk@ozlabs.org>

 ;
 ; Taken from:
 ;    PowerPC® Microprocessor Family:
 ;
 ; Taken from:
 ;    PowerPC® Microprocessor Family:


@@ -67,3 +68,32 @@ field: 56   Class (C)
 value:         0 big-endian
 value:         1 little-endian
 
 value:         0 big-endian
 value:         1 little-endian
 

+
+; The PowerPC Architecture:
+; A Specification For A New Family Of RISC Processors
+; Book III PowerPC Operating Environment Architecture
+
+; Section 2.2.3 Machine State Register (MSR)
+[MSR_32]
+name: PowerPC Machine State Register
+field: 13 Power Management Enable (POW)
+field: 15 Little-Endian Exception Mode (ILE)
+field: 16 External Interrupt Enable (EE)
+field: 17 Problem State (PR)
+value:         0 privileged state
+value:         1 problem state
+field: 18 Floating-Point Available (FP)
+field: 19 Machine Check Interrupt Enable (ME)
+field: 20,23 Floating-Point Exception Mode (FE)
+value:          0 ignore exceptions
+value:          1 imprecise nonrecoverable
+value:          2 imprecise recoverable
+value:          3 precise
+field: 21 Single-Step Trace Enable (SE)
+field: 22 Branch Trace Enable (BE)
+field: 26 Instruction Relocate (IR)
+field: 27 Data Relocate (DR)
+field: 30 Recoverable Interrupt (RI)
+field: 31 Little-Endian Mode (LE)
+value:         0 big-endian
+value:         1 little-endian