Minor line-wrap update

[bitfield] / conf / powerpc.conf

diff --git a/conf/powerpc.conf b/conf/powerpc.conf
index c3268a100c1f33b3de44df80a04c7a4abb100ede..1303d93c27c37af07dcb3fdce734dec0334e7cf2 100644 (file)
--- a/conf/powerpc.conf
+++ b/conf/powerpc.conf
@@ -2,17 +2,28 @@
 ;
 ; Contributors:
 ;  Michael Neuling <mikey@neuling.org>
+;
+; Taken from:
+;    PowerPC® Microprocessor Family:
+;    The Programming Environments Manual for 32 and 64-bit Microprocessors
+;    Version 2.3
+;    http://www.power.org/resources/downloads/PowerISA_203.Public.pdf
+;
 
-[MSR]
+; Section 2.3.1 Machine State Register (MSR)
+[MSR_64]
 name: PowerPC Machine State Register
 field:  0 64-bit mode (SF)
 value:         0 32-bit mode
 value:         1 64-bit mode
+field:  2 Exception 64-bit mode
 field:  3 Hypervisor State (HV)
+field: 45 Power Management Enable (POW)
+field: 47 Little-Endian Exception Mode (ILE)
 field: 48 External Interrupt Enable (EE)
 field: 49 Problem State (PR)
-value:  0 privileged state
-value:  1 problem state
+value:         0 privileged state
+value:         1 problem state
 field: 50 Floating-Point Available (FP)
 field: 51 Machine Check Interrupt Enable (ME)
 field: 52,55 Floating-Point Exception Mode (FE)
@@ -30,12 +41,14 @@ field: 63 Little-Endian Mode (LE)
 value:         0 big-endian
 value:         1 little-endian
 
+; Section 8, Instruction slbmte
 [SLB_E]
 name: PowerPC SLB ESID Entry
 field: 0:35  Effective segment ID (ESID)
 field: 36    Valid (V)
 field: 52:63 Index
 
+; Section 8, Instruction slbmte
 [SLB_V]
 name: PowerPC SLB VSID Entry
 field: 0:1  Segment size selector (B)