return None
@staticmethod
- def parse_bitfield(line):
+ def mask_and_shift_to_bits(width, mask, shift):
+ bits = []
+ val = mask << shift
+ for i in range(0, width):
+ if mask & (1 << i):
+ bits.append(width - i - 1 - shift)
+ return bits
+
+ @staticmethod
+ def parse_bitfield(line, reg):
a = line.split(None, 1)
if len(a) != 2:
return None
bits = []
for s in range_str.split(','):
if ':' in s:
- (start, end) = s.split(':')
- bits.extend(range(int(start), int(end) + 1, 1))
+ (start, end) = map( \
+ lambda s: reg.bit_number(int(s)),
+ s.split(':'))
+ start = reg.bit_number(int(start))
+ end = reg.bit_number(int(end))
+ bits.extend(range(start, end + 1, 1))
+ elif '<<' in s:
+ (mask, shift) = map(lambda s: int(s.strip()),
+ s.split('<<'))
+ bits.extend(bitfield.mask_and_shift_to_bits( \
+ reg.width, mask, shift))
else:
- bits.append(int(s))
-
+ bits.append(reg.bit_number(int(s)))
+
return bitfield(bits, name)
+
+
@staticmethod
def parse_value(line):
a = line.split(None, 1)
return a
class register:
- def __init__(self, id, name, width):
+ bit_0_is_msb = 0
+ bit_0_is_lsb = 1
+
+ def __init__(self, id):
self.id = id
- self.name = name
- self.width = width
self.fields = []
+ # set defaults
+ self.name = None
+ self.bit_order = self.bit_0_is_msb
+ self.width = 64
def add_field(self, field):
self.fields.append(field)
% (name_width, field.name, v)
return str
+ def bit_number(self, number):
+ if self.bit_order == self.bit_0_is_lsb:
+ number = self.width - 1 - number
+ return number
+
def list_regs(regs):
for (id, r) in regs.iteritems():
print "%18s : %s" % (id, r.name)
tokens = bnf.parseString(f.read())
+ order_map = {'bit-0-is-lsb': register.bit_0_is_lsb,
+ 'bit-0-is-msb': register.bit_0_is_msb,
+ 'ibm': register.bit_0_is_msb,
+ 'default': register.bit_0_is_msb}
+
for tok in tokens:
ts = tok.asList()
id = ts.pop(0)
raise ConfigurationError(file,
"Register %s is already defined" % id)
- # default to 64 bit registers
- width = 64
- name = None
+ reg = register(id)
+
alias_id = None
fields = []
for t in ts:
if t[0] == 'name':
name = t[1]
- name = name.strip()
+ reg.name = name.strip()
elif t[0] == 'width':
- width = int(t[1])
+ reg.width = int(t[1])
elif t[0] == 'field':
- f = bitfield.parse_bitfield(t[1])
+ f = bitfield.parse_bitfield(t[1], reg)
if f is None:
raise ConfigurationError(file,
"Invalid field in %s" % id)
"Invalid value in %s" % id)
fields[-1].add_value(v[0], v[1])
+ elif t[0] == 'order':
+ if len(fields) != 0:
+ raise ConfigurationError(file,
+ ("bit order defined after " \
+ + "fields in %s") % id)
+
+ order_str = t[1].strip().lower()
+ order_str = order_str.replace(' ', '-')
+
+ if order_str not in order_map.keys():
+ raise ConfigurationError(file,
+ "Invalid bit order %s in %s" % \
+ (order_str, id))
+ reg.bit_order = order_map[order_str]
+
elif t[0] == 'alias':
alias_id = t[1].strip()
if alias_id is not None:
- if name is not None or fields != []:
+ if reg.name is not None or fields != []:
raise ConfigurationError(file, ("Definiton " \
+ "for %s is an alias, but has other " \
+ "attributes") % id)
"non-existent register %s (from %s)" \
% (alias_id, id))
- regs[id] = regs[alias_id]
+ reg = regs[alias_id]
continue
- if name is None or name == '':
+ if reg.name is None or reg.name == '':
raise ConfigurationError(file,
"No name for entry %s" % id)
raise ConfigurationError(file,
"Register %s has no fields" % id)
- r = register(id, name, width)
for f in fields:
- r.add_field(f)
+ reg.add_field(f)
- regs[id] = r
+ regs[id] = reg
def parse_config_dir(data, dir, fnames):
(bnf, regs) = data
value_iter = args.__iter__()
else:
value_iter = iter(sys.stdin.readline, '')
-
+
try:
for value in value_iter:
decode_value(reg, value.strip(), options)
projects / bitfield / blobdiff