- for out_bit in range(0, out_len):
- in_bit = self.bits[out_bit]
+
+ if reg.bit_order == reg.bit_0_is_msb:
+ bit_pairs = zip(self.bits, range(0, out_len))
+ else:
+ bit_pairs = zip(self.bits, range(out_len - 1, -1, -1))
+
+ for (in_bit, out_bit) in bit_pairs: