Added 32-bit MSR to powerpc definitions

[bitfield] / bitfield

diff --git a/bitfield b/bitfield
index 3b34aeb5b7514befdd0b9edc277cec373f9997fa..8bb8d352d7663aafdfbeae782ff19e6063ad5c5c 100644 (file)
--- a/bitfield
+++ b/bitfield
@@ -48,6 +48,15 @@ class bitfield:
                        return self.values[value]
                return None
 
+       @staticmethod
+       def mask_and_shift_to_bits(width, mask, shift):
+               bits = []
+               val = mask << shift
+               for i in range(0, width):
+                       if mask & (1 << i):
+                               bits.append(width - i - 1 - shift)
+               return bits
+
        @staticmethod
        def parse_bitfield(line, reg):
                a = line.split(None, 1)
@@ -58,15 +67,24 @@ class bitfield:
                bits = []
                for s in range_str.split(','):
                        if ':' in s:
-                               (start, end) = s.split(':')
+                               (start, end) = map( \
+                                       lambda s: reg.bit_number(int(s)),
+                                       s.split(':'))
                                start = reg.bit_number(int(start))
                                end = reg.bit_number(int(end))
                                bits.extend(range(start, end + 1, 1))
+                       elif '<<' in s:
+                               (mask, shift) = map(lambda s: int(s.strip()),
+                                       s.split('<<'))
+                               bits.extend(bitfield.mask_and_shift_to_bits( \
+                                       reg.width, mask, shift))
                        else:
                                bits.append(reg.bit_number(int(s)))
  
                return bitfield(bits, name)
 
+
+
        @staticmethod
        def parse_value(line):
                a = line.split(None, 1)