Add support for hex (and octal) values

[bitfield] / bitfield

diff --git a/bitfield b/bitfield
index 8bb8d352d7663aafdfbeae782ff19e6063ad5c5c..7740ff2b0d375ebd049109ad4b7971e593faea2b 100644 (file)
--- a/bitfield
+++ b/bitfield
@@ -1,4 +1,4 @@
-#!/usr/bin/python2.4
+#!/usr/bin/env python
 #
 # Utility to decode register values
 # Copyright (c) 2006 Jeremy Kerr <jk@ozlabs.org>
@@ -29,7 +29,7 @@ class bitfield:
                return len(self.bits)
 
        def add_value(self, value, description):
-               self.values[int(value)] = description
+               self.values[int(value, 0)] = description
 
        def mask(self, reg_width, value):
                ret = 0
@@ -54,9 +54,13 @@ class bitfield:
                val = mask << shift
                for i in range(0, width):
                        if mask & (1 << i):
-                               bits.append(width - i - 1 - shift)
+                               bits.insert(0, width - i - 1 - shift)
                return bits
 
+       @staticmethod
+       def mask_to_bits(width, mask):
+               return bitfield.mask_and_shift_to_bits(width, mask, 0)
+
        @staticmethod
        def parse_bitfield(line, reg):
                a = line.split(None, 1)
@@ -78,9 +82,13 @@ class bitfield:
                                        s.split('<<'))
                                bits.extend(bitfield.mask_and_shift_to_bits( \
                                        reg.width, mask, shift))
+                       elif s.startswith('&'):
+                               mask = int(s[1:], 0)
+                               bits.extend(bitfield.mask_to_bits(reg.width, \
+                                                       mask))
                        else:
                                bits.append(reg.bit_number(int(s)))
- 
+
                return bitfield(bits, name)
 
 
@@ -125,7 +133,7 @@ class register:
                                str += "%*s: 0x%x\n" \
                                        % (name_width, field.name, v)
                return str
-       
+
        def bit_number(self, number):
                if self.bit_order == self.bit_0_is_lsb:
                        number = self.width - 1 - number
@@ -203,7 +211,7 @@ def parse_config(bnf, regs, file):
                                                "Invalid bit order %s in %s" % \
                                                (order_str, id))
                                reg.bit_order = order_map[order_str]
-                               
+
                        elif t[0] == 'alias':
                                alias_id = t[1].strip()
 
@@ -349,7 +357,7 @@ def main():
                value_iter = args.__iter__()
        else:
                value_iter = iter(sys.stdin.readline, '')
-               
+
        try:
                for value in value_iter:
                        decode_value(reg, value.strip(), options)