Fix bit-0-is-lsb ordering

[bitfield] / ChangeLog

diff --git a/ChangeLog b/ChangeLog
index 79dbd74d32e2921318dfb7cd3dd0df36206edd64..094262f37d4d2ae22ab85040230dcfca85312835 100644 (file)
--- a/ChangeLog
+++ b/ChangeLog
@@ -1,5 +1,8 @@
 version ??
+       * Add support for &mask syntax
        * Allow alternate (bit 0 is lsb) bit numbering scheme
+       * Add support for mask<<shift field definitions
+       * Add configuration for a few radeon registers
 
 version 0.2:
        * Add support for aliased definitions.