--- /dev/null
+; Definitions for the Cell Broadband Engine
+;
+; Contributors:
+; Jeremy Kerr <jk@ozlabs.org>
+
+[IOC_IOST_Origin]
+name: Cell IOMMU Segmentation Table Origin
+width: 64
+field: 0 Enable
+field: 22:51 IOST origin
+field: 52 HW
+field: 53 HL
+
+[IOC_IO_ExcpStat]
+name: Cell I/O Exception Status Register
+width: 64
+field: 0 Valid
+field: 1:2 Segment/Page Fault
+value: 0 none
+value: 1 page fault
+value: 2 undefined
+value: 3 segment fault
+field: 29:51 Address
+field: 52 RW
+value: 0 write
+value: 1 read
+field: 53:63 IOID
+
+[IOC_IOCmd_Cfg]
+name: Cell IOCmd Configuration
+field: 0:15 IOC Timeout
+field: 16 TE
+field: 17 Enable tokens
+field: 18 Read-modify-write
+field: 19 SXT
+field: 20 Node ID 0
+field: 21:31 IOID0
+field: 32:34 CVCID0
+filed: 35 IR0
+field: 36 E0
+field: 37 Node ID 1
+field: 38:48 IOID1
+field: 49:51 CVCID1
+filed: 52 IR1
+field: 53 E1
+field: 54:57 Starvation count 1
+field: 58 AAR
+field: 59 AAA
+field: 60 Disable ageing
+field: 61 Read intervention
+
+
+[IOC_STE]
+name: Cell IOMMU Segmentation Table Entry
+field: 0 Valid
+field: 1 Hint
+field: 2:51 IOPT Base RPN
+field: 52:58 NPPT
+field: 60:63 Page size
+
+[IOC_PTE]
+name: Cell IOMMU Page Table Entry
+field: 0:1 Page protection
+value: 0 no access
+value: 1 read
+value: 2 write
+value: 3 read & write
+field: 2 Coherence required
+field: 3:4 Storage ordering
+value: 0 none
+value: 1 reserved
+value: 2 writes
+value: 3 reads & writes
+field: 5:51 RPN
+field: 52:63 IOID
+
+[IOC_IOPT_CacheInvd]
+name: Cell IOC IOPT Cache Invalidate
+field: 0:10 Number of entries
+field: 22:60 IOPTE real address
+field: 63 Busy
+
+[SPU_Status]
+name: Cell SPU Status
+width: 32
+field: 0:15 Stop-and-signal status
+field: 21 Isolate exit
+field: 22 Isolate load
+field: 24 Isolated mode
+field: 26 Stopped: invalid instruction
+field: 27 Stopped: single-step mode
+field: 28 Waiting on blocked channel
+field: 29 Stopped: halt instruction
+field: 30 Stopped: stop-and-signal
+field: 31 Running
+
+[MFC_SR1]
+name: Cell MFC State Register 1
+width: 64
+field: 57 Software/hardware page tables
+field: 58 Master run control
+value: 0 Stopped
+value: 1 Running
+field: 59 MFC Translation
+field: 60 Problem state
+field: 62 Bus tlbie
+field: 63 Local store real address
+
--- /dev/null
+; Definitions for the PowerPC architecture
+;
+; Contributors:
+; Michael Neuling <mikey@neuling.org>
+
+[MSR]
+name: PowerPC Machine State Register
+field: 0 64-bit mode (SF)
+value: 0 32-bit mode
+value: 1 64-bit mode
+field: 3 Hypervisor State (HV)
+field: 48 External Interrupt Enable (EE)
+field: 49 Problem State (PR)
+value: 0 privileged state
+value: 1 problem state
+field: 50 Floating-Point Available (FP)
+field: 51 Machine Check Interrupt Enable (ME)
+field: 52,55 Floating-Point Exception Mode (FE)
+value: 0 ignore exceptions
+value: 1 imprecise nonrecoverable
+value: 2 imprecise recoverable
+value: 3 precise
+field: 53 Single-Step Trace Enable (SE)
+field: 54 Branch Trace Enable (BE)
+field: 58 Instruction Relocate (IR)
+field: 59 Data Relocate (DR)
+field: 61 Performance Monitor Mark (PMM)
+field: 62 Recoverable Interrupt (RI)
+field: 63 Little-Endian Mode (LE)
+value: 0 big-endian
+value: 1 little-endian
+
+[SLB_E]
+name: PowerPC SLB ESID Entry
+field: 0:35 Effective segment ID (ESID)
+field: 36 Valid (V)
+field: 52:63 Index
+
+[SLB_V]
+name: PowerPC SLB VSID Entry
+field: 0:1 Segment size selector (B)
+value: 0 256MB
+value: 1 1TB
+value: 2 reserved
+value: 3 reserved
+field: 2:51 Virtual segment ID (VSID)
+field: 52 Supervisor state storage key (Ks)
+field: 53 Problem state storage key (Kp)
+field: 55,58,59 Virtual page size selector
+value: 0 4KB (Unless PTE specifies 64KB) (MPS)
+value: 5 64KB (Provided PTE specifies 64KB) (MPS)
+field: 54 No-execute segment (N)
+field: 56 Class (C)
+value: 0 big-endian
+value: 1 little-endian
+