This change adds a new syntax for bitfield definitions:
field: &0xff00 top 16-bits
This allows a mask (rather than mask << shift) value to be specified.
Signed-off-by: Jeremy Kerr <jk@ozlabs.org>
+ * Add support for &mask syntax
* Allow alternate (bit 0 is lsb) bit numbering scheme
* Add support for mask<<shift field definitions
* Add configuration for a few radeon registers
* Allow alternate (bit 0 is lsb) bit numbering scheme
* Add support for mask<<shift field definitions
* Add configuration for a few radeon registers
bits.insert(0, width - i - 1 - shift)
return bits
bits.insert(0, width - i - 1 - shift)
return bits
+ @staticmethod
+ def mask_to_bits(width, mask):
+ return bitfield.mask_and_shift_to_bits(width, mask, 0)
+
@staticmethod
def parse_bitfield(line, reg):
a = line.split(None, 1)
@staticmethod
def parse_bitfield(line, reg):
a = line.split(None, 1)
s.split('<<'))
bits.extend(bitfield.mask_and_shift_to_bits( \
reg.width, mask, shift))
s.split('<<'))
bits.extend(bitfield.mask_and_shift_to_bits( \
reg.width, mask, shift))
+ elif s.startswith('&'):
+ mask = int(s[1:], 0)
+ bits.extend(bitfield.mask_to_bits(reg.width, \
+ mask))
else:
bits.append(reg.bit_number(int(s)))
else:
bits.append(reg.bit_number(int(s)))