+
+; The PowerPC Architecture:
+; A Specification For A New Family Of RISC Processors
+; Book III PowerPC Operating Environment Architecture
+
+; Section 2.2.3 Machine State Register (MSR)
+[MSR_32]
+name: PowerPC Machine State Register
+field: 13 Power Management Enable (POW)
+field: 15 Little-Endian Exception Mode (ILE)
+field: 16 External Interrupt Enable (EE)
+field: 17 Problem State (PR)
+value: 0 privileged state
+value: 1 problem state
+field: 18 Floating-Point Available (FP)
+field: 19 Machine Check Interrupt Enable (ME)
+field: 20,23 Floating-Point Exception Mode (FE)
+value: 0 ignore exceptions
+value: 1 imprecise nonrecoverable
+value: 2 imprecise recoverable
+value: 3 precise
+field: 21 Single-Step Trace Enable (SE)
+field: 22 Branch Trace Enable (BE)
+field: 26 Instruction Relocate (IR)
+field: 27 Data Relocate (DR)
+field: 30 Recoverable Interrupt (RI)
+field: 31 Little-Endian Mode (LE)
+value: 0 big-endian
+value: 1 little-endian
+
+; POWER ISA(tm) Book III-S
+; Section 5.7.6.1 Page Table
+
+[PTE_V]
+name: Page Table Entry, Dword 0
+field: 0:1 Segment Size (B)
+value: 0 256MB
+value: 1 1TB
+value: 2 reserved
+value: 3 reserved
+field: 2:56 Abbreviated Virtual Page Number (AVPN)
+field: 57:60 Software bits (SW)
+field: 61 Virtual page size (L)
+value: 0 4KB
+value: 1 large page
+field: 62 Hash function identifier (H)
+field: 63 Valid (V)
+
+[PTE_R]
+name: Page Table Entry, Dword 1
+field: 2:43 Appreviated Real Page Number (ARPN)
+field: 44:51 Large page size selector (LP)
+field: 54 Address Compare bit (AC)
+field: 55 Reference bit (R)
+field: 56 Change bit (C)
+field: 57 Storage control bit (W)
+field: 58 Storage control bit (I)
+field: 59 Storage control bit (M)
+field: 60 Storage control bit (G)
+field: 61 No-execute page (N)
+field: 62:63 Page protection bits (PP)
+value: 0 Key=0 read/write K=1 no access
+value: 1 Key=0 read/write K=1 read only
+value: 2 Key=0 read/write K=1 read/write
+value: 3 Key=0 read only K=1 read only