`timescale 1ns / 100ps

/*
 * m68k CPU to internal bus interface
 * 
 * Devices & Memory bus protocol:
 *
 * We implement a two phase bus protocol to the outside world
 * 
 * - Address phase (phase 0) corresponds to CPU S4 & S5
 *
 * - Data phase (phase 1) corrsponds to CPU S6 & S7
 * 
 * Devices shall typically act on the clock edge at the begining of each
 * phase, tho phase 0 can generally be ignored for simple devices. Phase 0
 * shall not cause any action to be committed, but the phase 0 edge is
 * when we sample the "ack" signal which allows transition to phase 1.
 * 
 * Thus phase 0 is only here to allow devices to delay/hold the bus, which
 * is used by SCSI to make blind transfer reliable and our memory interface
 * because I'm an idiot and didn't properly interleave CPU and video. I will
 * probably use it from the SWIM interface too when transfering raw data.
 * 
 * Here are the signal that are valid at phase 0 and phase 1 clock
 * edges. I also noted whether those signals remain valid in the clock
 * cycle following phase 1 clock edge (ie, during phase 1 / S6/S7) since
 * some devices such as memory rely on these.
 * 
 *  Signal	Phase 0 clk		Phase 1 clk		Phase 1
 * 
 *  bus_cs_xxx	yes			yes			no (*)
 *  bus_we	yes			yes			yes
 *  bus_ube/lbe	no (**)			yes			no (**)
 *  bus_addr	yes			yes			yes
 *  bus_wdata	yes			yes			no (***)
 *  bus_phase	0			1			0
 * 
 *  from device:
 * 
 *  bus_ack	no			yes			no (****)
 *  bus_rdata	no			yes			n/a
 * 
 * (*) CS is lowered during phase 1 so that the next clock edge doesn't
 *     get mistaken for a new phase 0 cycle.
 * 
 * (**) For a CPU initiated cycle, bus_ube/lbe are directly sourced from
 *      the m68k's _UDS and _LDS lines, which for a write are only asserted
 *      in S4, so right -after- phase 0 clock edge, and are released in S7
 *      right after the negative edge following phase 1 clock edge. The
 *      memory interface routes those signal directly to the SRAM, the
 *      timing should be just right (with something like 15ns margin), but
 *      we might want to establish constraints in the FPGA design to ensure
 *      that. Alternatively, we could latch them on the clock negative edge
 *      and maintain them all the way during phase 1 but that isnt necessary
 *      for now I believe.
 * 
 * (***) For a CPU initiate cycle, bus_wdata is sources directly from the
 *       m68k's data bus, which becomes invalid in S7, after the negedge
 *       of the clock. There's a 15ns valid time between UDS/LDS going
 * 	 up and data becoming invalid on a 16Mhz CPU, but here too we
 *       might want to add constraints to the synthesis tool to guarantee
 *       we stay within the margin.
 * 
 * (****) The CPU DTACK is set from bus_ack and sampled asynchronously
 *        during phase 0 on the negative edge of the clock (end of S4),
 *        and by our CPU interface logic on phase 1 clk to validate
 * 	  actually going into phase 1 (else we remain in phase 0).
 * 	  Thus dumb devices can just wire CS to ACK and devices that
 *        want to hold the bus can do so by delaying ACK keeping the
 *        interface in phase 0.
 * 
 * WARNING: While in phase 0, the CPU interface might decide to switch to
 *          another master (the SPI interface is the only one for now),
 *          so devices shouldn't commit/latch anything with the assumption
 *          that a subsequent phase 0 will provide the same cs/address/...
 *          signals. However, if a device does ack, then going into phase 1
 *          on the next cycle is guaranteed.
 */

/* Backbus interface registers
 *
 * WARNING: Writing to the ADDR, DATA and MISC latches should only be
 * done while the bus is in stopped state. If an attempt is made to
 * write a latch that the CPU tries to update in the same cycle, the CPU
 * wins and the SPI write is lost.
 * 
 * Similarily, reading from those latches may result in inconsistent
 * values if done while the CPU interface is runnig as the SPI
 * interface will latch the data at some "random" time after the
 * strobe
 */
`define CPUINTF_REG_ADDR0	0
`define CPUINTF_REG_ADDR1	1
`define CPUINTF_REG_ADDR2	2
`define CPUINTF_REG_DATA0	3
`define CPUINTF_REG_DATA1	4
`define CPUINTF_REG_MISC	5 /* bit 2: _UDS, bit 1: _LDS, bit 0: R_W */
`define CPUINTF_REG_CTRL	6
`define   CPUINTF_CTRL_STOP_BIT		0 /* Stop CPU */
`define   CPUINTF_CTRL_RUN_BIT		1 /* Run CPU */
`define   CPUINTF_CTRL_CYCLE_BIT	2 /* Issue an SPI generated bus cycle */
`define   CPUINTF_CTRL_BKEN_BIT		6 /* Sticky, set with RUN to enable bkpt */
`define   CPUINTF_CTRL_STEP_BIT		7 /* Sticky, set with RUN to single step */
`define CPUINTF_REG_STAT	7 /* bus state machine */
`define CPUINTF_REG_BKPT0	8
`define CPUINTF_REG_BKPT1	9
`define CPUINTF_REG_BKPT2	10

module cpu_intf(input			sysclk,
		input			reset,

		/* m68k CPU pins */
		inout [15:0]		cpu_data,
		input [23:1]		cpu_addr,
		input			_cpu_as,
		input			_cpu_uds,
		input			_cpu_lds,
		input			cpu_r_w,
		output			_cpu_dtack,
		/*inout			_cpu_reset,*/

		/* Backbus interface */
		input [5:0] 		bb_addr,
		input [7:0] 		bb_wdata,
		output[7:0]	 	bb_rdata,
		input			bb_strobe,
		input			bb_wr,
		
		/* Common device bus interface */
		output [23:1]		bus_addr,
		output [15:0]		bus_wdata,
		output			bus_ube,
		output			bus_lbe,
		output			bus_we,
		output			bus_phase,

		/* Per-device CS, ACK and data input */
		output			bus_cs_ram,
		output			bus_cs_rom,
		input			bus_ack_mem,
		input [15:0]		bus_rdata_mem, /* RAM and ROM */
		output			bus_cs_scsi,
		input			bus_ack_scsi,
		input [7:0]		bus_rdata_scsi,
		output			bus_cs_scc,
		input			bus_ack_scc,
		input [7:0]		bus_rdata_scc,
		output			bus_cs_via,
		input			bus_ack_via,
		input [7:0]		bus_rdata_via,
		output			bus_cs_iwm,
		input			bus_ack_iwm,
		input [7:0]		bus_rdata_iwm,

		/* Global control signals */
		input			rom_ovl /* from VIA */
);
	
	/* For autovector simulation since we have no _avec pin */
	wire		cs_ivec;

	/* No target for a bus request */
	wire		cs_nack;	

	/* Bus request signal, activates chip selects */
	wire		bus_req;

	/* Cumulative ack result from devices */
	wire		bus_ack;	

	/* Address data and control latches (for spy and SPI ops) */
	reg [23:1] 	addr_latch;
	reg [15:0] 	data_latch;
	reg 		_uds_latch;
	reg 		_lds_latch;
	reg 		r_w_latch;

	/* SPI control register */
	reg [7:0] 	spi_ctrl;	

	/* Data bus mux */
	wire [15:0] 	bus_rdata;	/* Demuxed from devices */

	/* Breakpoint */
	reg [23:1] 	addr_bkpt;
	wire		addr_bphit;
	
	/* Signals from the SPI interface */
	wire		spi_wreg;	
	wire		spi_reg_addr0;
	wire		spi_reg_addr1;
	wire		spi_reg_addr2;
	wire		spi_reg_data0;
	wire		spi_reg_data1;
	wire		spi_reg_misc;
	wire		spi_reg_ctrl;
	wire		spi_reg_stat;
	wire		spi_reg_bkpt0;
	wire		spi_reg_bkpt1;
	wire		spi_reg_bkpt2;
	
	/* State machine */
	localparam bi_state_idle = 8'h84; /* idle, addr & r_w from CPU */
	localparam bi_state_cpu0 = 8'h85; /* cpu S4,S5 */
	localparam bi_state_cpu1 = 8'h82; /* cpu S6,S7 */
	localparam bi_state_spip = 8'h44; /* spi control, prep addr & r_w */
	localparam bi_state_spi0 = 8'h45; /* spi control, pseudo S4,S5 */
	localparam bi_state_spi1 = 8'h42; /* spi control, psuedo S6,S7 */
	localparam bi_state_stop = 8'h48; /* spi control, stopped */

	/* Note on individual state bits::
	    - 7 : CPU cycle
	    - 6 : SPI cycle
	    - 5 : unused
	    - 4 : unused
	    - 3 : stopped
	    - 2 : CS set based on _AS (or 1 for SPI)
	    - 1 : allow cpu data input and force dtack
	    - 0 : bus phase at next clock
	 
	   You may notice that we drop CS on CPU phase S6,S7. We must do
	   that for SPI as we must not have more than 2 phases with CS set
	   in one cycle, but we could leave bit 2 set for the CPU in that
	   stage as _AS is supposed to go down... doesn't matter much tho
	 */
	reg [7:0] 	state;
	
	/* Instanciate address decoder */	
	addr_decode decode0(.addr(bus_addr),
			    .req(bus_req),
			    .rom_ovl(rom_ovl),
			    .cs_ram(bus_cs_ram),
			    .cs_rom(bus_cs_rom),
			    .cs_scsi(bus_cs_scsi),
			    .cs_scc(bus_cs_scc),
			    .cs_iwm(bus_cs_iwm),
			    .cs_via(bus_cs_via),
			    .cs_ivec(cs_ivec),
			    .cs_nack(cs_nack));

	/* Generate bus address. Avoid propagating z state from the
	 * CPU to the FPGA by gating with _cpu_as
	 */
	assign bus_addr = (!state[7]) ? addr_latch :
			  _cpu_as ? 22'h3fffff : cpu_addr;

	/* Data bus to CPU is hi-z unless CPU has r_w up -and- we are
	 * in phase 1. Should keep us safe from shorts. We always feed
	 * the CPU from the data latch
	 */
	assign cpu_data = (cpu_r_w & state[1]) ? data_latch : 16'bz;

	/* Data bus and control signals to devices */
	assign bus_wdata = state[7] ? cpu_data : data_latch;
	assign bus_ube = ~(state[7] ? _cpu_uds : _uds_latch);
	assign bus_lbe = ~(state[7] ? _cpu_lds : _lds_latch);
	assign bus_we = ~(state[7] ? cpu_r_w : r_w_latch);

	/* Address decoder's enable signal which controls CS signals */
	assign bus_req = state[2] & (state[6] | ~_cpu_as);

	/* Bus phase output straight off the state machine */
	assign bus_phase = state[0];

	/* Data from devices demux (and generate autovector value) */
	assign bus_rdata = (bus_cs_ram | bus_cs_rom) ? bus_rdata_mem :
			   bus_cs_scsi ? { bus_rdata_scsi, 8'h0 } :
			   bus_cs_scc  ? { bus_rdata_scc, 8'h0 } :
			   bus_cs_via  ? { bus_rdata_via, 8'h0 } :
			   bus_cs_iwm  ? { 8'h0, bus_rdata_iwm } :
			   cs_ivec ? { 11'b0, 2'b11, bus_addr[3:1] } :
`ifdef __IVERILOG__
			   16'hbeef;
`else	
			   16'b1111_1111_1111_1111;
`endif	

	/* We OR all acks, devices shall not set ack if their CS isn't set
	 * additionally, we ack for ivec and nack signals from the decoder
	 * as those are handled locally
	 */
	assign bus_ack = bus_ack_mem |
			 bus_ack_scsi |
			 bus_ack_scc |
			 bus_ack_via |
			 bus_ack_iwm |
			 cs_ivec | cs_nack;
`ifdef __IVERILOG__
	/* Debug stuff, sim only */
	always@(posedge sysclk or posedge reset) begin
		if (cs_nack && bus_we && bus_phase) begin
			$write("%c", bus_wdata[15:8]);
		end
	end
`endif


	/* Breakpoint check */
	assign addr_bphit = (cpu_addr == addr_bkpt) &
			    spi_ctrl[`CPUINTF_CTRL_BKEN_BIT];
			    
	/* Generate _DTACK for CPU cycles only. Note that the doc is
	 * unlcear as to whether we must keep it asserted until
	 * _AS goes back up or whether we can take it off as soon as
	 * state S5 or or later is reached.
	 * Better safe than sorry, we keep it down all the way for now
	 * at least until I have more than my crude sim to test with.
	 */
	assign _cpu_dtack = _cpu_as | ~state[7] | /* CPU cycle and AS asserted */
			    (~state[1] & ~(state[0] & bus_ack));
	/* Bus state machine */
	always@(posedge sysclk or posedge reset) begin
		if (reset) begin
			state <= bi_state_stop;
		end else
		  case(state)
			  bi_state_idle: begin
				  /* SPI takeover */
				  if (spi_ctrl[`CPUINTF_CTRL_STOP_BIT])
					  state <=  bi_state_stop;

				  /* If the CPU is trying to start a cycle,
				   * move up. CS will already have been generated
				   * asynchronously on the bus interface. We also
				   * detect breakpoints there
				   */
				  else if (!_cpu_as) begin
					  if (addr_bphit)
					    state <= bi_state_stop;
					  else
					    state <= bi_state_cpu0;
				  end 			  

				  /* If the CPU is idle and we are stepping,
				   * we stop again
				   */
				  else if (spi_ctrl[`CPUINTF_CTRL_STEP_BIT])
				    state <= bi_state_stop;
			  end
			  bi_state_cpu0: begin
				  /* We got an ack from the device, move to
				   * phase 1
				   */
				  if (bus_ack)
				    state <= bi_state_cpu1;

				  /* No ack, another try at SPI takeover */
				  else if (spi_ctrl[`CPUINTF_CTRL_STOP_BIT])
				    state <=  bi_state_stop;
			  end
			  bi_state_cpu1: begin
				  /* If stepping, stop now */
				  if (spi_ctrl[`CPUINTF_CTRL_STEP_BIT])
				    state <=  bi_state_stop;

				  /* Back to idle */
				  else
				    state <= bi_state_idle;
			  end
			  bi_state_spip: begin
				  state <= bi_state_spi0;
			  end
			  bi_state_spi0: begin
				  if (bus_ack)
				    state <= bi_state_spi1;
			  end
			  bi_state_spi1: begin
				  state <= bi_state_stop;
			  end
			  bi_state_stop: begin
				  /* Restart CPU */
				  if (spi_ctrl[`CPUINTF_CTRL_RUN_BIT])
				    state <= bi_state_idle;

				  /* Start a simulated cycle */
				  else if (spi_ctrl[`CPUINTF_CTRL_CYCLE_BIT])
				    state <= bi_state_spip;
			  end
		  endcase
	end

	/* Some SPI backbus interface combo decode logic */
	assign spi_wreg = bb_strobe && bb_wr;
	assign spi_reg_addr0 = bb_addr[3:0] == `CPUINTF_REG_ADDR0;
	assign spi_reg_addr1 = bb_addr[3:0] == `CPUINTF_REG_ADDR1;
	assign spi_reg_addr2 = bb_addr[3:0] == `CPUINTF_REG_ADDR2;
	assign spi_reg_data0 = bb_addr[3:0] == `CPUINTF_REG_DATA0;
	assign spi_reg_data1 = bb_addr[3:0] == `CPUINTF_REG_DATA1;
	assign spi_reg_misc  = bb_addr[3:0] == `CPUINTF_REG_MISC;
	assign spi_reg_ctrl  = bb_addr[3:0] == `CPUINTF_REG_CTRL;
	assign spi_reg_stat  = bb_addr[3:0] == `CPUINTF_REG_STAT;
	assign spi_reg_bkpt0 = bb_addr[3:0] == `CPUINTF_REG_BKPT0;
	assign spi_reg_bkpt1 = bb_addr[3:0] == `CPUINTF_REG_BKPT1;
	assign spi_reg_bkpt2 = bb_addr[3:0] == `CPUINTF_REG_BKPT2;

	/* Latches used by SPI interface to latch address/data
	 * when generating cycles. When under CPU control, they
	 * latch the last CPU cycle for single step mode
	 */

	/* Address latch */
	always@(posedge sysclk or posedge reset) begin
		if (reset) begin
			addr_latch <= 0;
		end else begin
			/* Latch the CPU address for any CPU cycle in phase 0 */
			if (state[7]) begin
				if (state[0])
				  addr_latch <= cpu_addr;
			end else if (spi_wreg) begin
				/* Or fill from SPI */
				if (spi_reg_addr0)
				  addr_latch[23:16] <= bb_wdata;
				else if (spi_reg_addr1)
				  addr_latch[15:8] <= bb_wdata;
				else if (spi_reg_addr2)
				  addr_latch[7:1] <= bb_wdata[7:1];
			end			
		end
	end

	/* Data latch. The CPU always feed from this, we latch the data
	 * from the device at phase 1 clock edge
	 */
	always@(posedge sysclk or posedge reset) begin
		if (reset) begin
			data_latch <= 0;
		end else begin
			/* Latch the bus data in phase 1 clock. Don't
			 * bother with ack, we'll latch a fresh value
			 * later if not set
			 */
			if (state[0]) begin
				if (bus_we)
				  data_latch <= bus_wdata;
				else
				  data_latch <= bus_rdata;
			/* Else handle write from SPI */
			end else if (spi_wreg) begin
				if (spi_reg_data0)
				  data_latch[15:8] <= bb_wdata;
				else if (spi_reg_data1)
				  data_latch[7:0] <= bb_wdata;
			end			
		end
	end

	/* Misc latches (uds/lds/rw) */
	always@(posedge sysclk or posedge reset) begin
		if (reset) begin
			_uds_latch <= 0;			
			_lds_latch <= 0;
			r_w_latch <= 0;			
		end else begin
			/* Latch the CPU misc for any CPU cycle in phase 0 */
			if (state[7]) begin
				if (state[0]) begin
					_uds_latch <= _cpu_uds;
					_lds_latch <= _cpu_lds;
					r_w_latch <= cpu_r_w;
				end				
			end else if (spi_wreg) begin
				/* Or fill from SPI */
				if (spi_reg_misc) begin
					_uds_latch <= bb_wdata[2];
					_lds_latch <= bb_wdata[1];
					r_w_latch <= bb_wdata[0];
				end
			end
		end
	end

	/* SPI control register */
	always@(posedge sysclk or posedge reset) begin
		if (reset) begin
			spi_ctrl <= 0;
		end else begin
			/* Stop bit cleared whenever we are stopped */
			if (state[3])
			  spi_ctrl[`CPUINTF_CTRL_STOP_BIT] <= 0;
			/* Run bit cleared if we are in any CPU cycle */
			if (state[7])
			  spi_ctrl[`CPUINTF_CTRL_RUN_BIT] <= 0;
			/* Cycle bit cleared when we are in an SPI cycle */
			if (state[6])			 
			  spi_ctrl[`CPUINTF_CTRL_CYCLE_BIT] <= 0;

			/* Now write logic from SPI. All bits are OR except
			 * for step and bken that is sticky
			 */
			if (spi_wreg && spi_reg_ctrl) begin
				spi_ctrl[2:0] <= spi_ctrl[2:0] | bb_wdata[2:0];
				spi_ctrl[7:6] <= bb_wdata[7:6];
			end
		end		
	end	

	/* Breakpoint register */
	always@(posedge sysclk or posedge reset) begin
		if (reset) begin
			addr_bkpt <= 0;
		end else begin
			if (spi_wreg) begin
				/* Or fill from SPI */
				if (spi_reg_bkpt0)
				  addr_bkpt[23:16] <= bb_wdata;
				else if (spi_reg_bkpt1)
				  addr_bkpt[15:8] <= bb_wdata;
				else if (spi_reg_bkpt2)
				  addr_bkpt[7:1] <= bb_wdata[7:1];
			end			
		end
	end
	
	/* SPI backbus register read logic */
	assign bb_rdata = spi_reg_addr0 ? addr_latch[23:16] :
			  spi_reg_addr1 ? addr_latch[15:8] :
			  spi_reg_addr2 ? { addr_latch[7:1], 1'b0 } :
			  spi_reg_data0 ? data_latch[15:8] :
			  spi_reg_data1 ? data_latch[7:0] :
			  spi_reg_misc  ? { 5'b0, _uds_latch, _lds_latch,
					    r_w_latch } :
			  spi_reg_ctrl  ? spi_ctrl :
			  spi_reg_stat  ? state :
			  0;
endmodule