From: Ahmed Samy <f.fallen45@gmail.com>
Date: Mon, 11 Nov 2013 16:21:31 +0000 (+0200)
Subject: cpuid: parse L1 cache information for AMD.
X-Git-Url: http://git.ozlabs.org/?p=ccan;a=commitdiff_plain;h=39c84ebc38cc5d1180eec154ec1e748d2ddc1682

cpuid: parse L1 cache information for AMD.

Also take out additional feature information from processor information
and feature bits since they can be tested using cpuid_test_feature() and
cpuid_has_feature()

Signed-off-by: Ahmed Samy <f.fallen45@gmail.com>
---

diff --git a/ccan/cpuid/cpuid.c b/ccan/cpuid/cpuid.c
index 2ea522b7..a64b1575 100644
--- a/ccan/cpuid/cpuid.c
+++ b/ccan/cpuid/cpuid.c
@@ -310,14 +310,11 @@ void cpuid(cpuid_t info, uint32_t *buf)
 			buf[3] = (eax >> 16) & 0x0F; 	/* Extended Model.  */
 			buf[4] = (eax >> 24) & 0x0F; 	/* Extended Family.  */
 
-			buf[5] = edx; 			/* Feature flags #1.  */
-			buf[6] = ecx; 			/* Feature flags #2.  */
-
 			/* Additional Feature information.  */
-			buf[7] = ebx & 0xFF;
-			buf[8] = (ebx >> 8) & 0xFF;
-			buf[9] = (ebx >> 16) & 0xFF;
-			buf[10] = (ebx >> 24) & 0xFF;
+			buf[5] = ebx & 0xFF;
+			buf[6] = (ebx >> 8) & 0xFF;
+			buf[7] = (ebx >> 16) & 0xFF;
+			buf[8] = (ebx >> 24) & 0xFF;
 			break;
 		case CPUID_CACHE_AND_TLBD_INFO:
 			buf[0] = eax;
@@ -330,10 +327,25 @@ void cpuid(cpuid_t info, uint32_t *buf)
 			buf[1] = ecx;
 			break;
 		case CPUID_L1_CACHE_AND_TLB_IDS:
-			buf[0] = eax;
-			buf[1] = ebx;
-			buf[2] = ecx;
-			buf[3] = edx;
+			buf[0] = eax & 0xFF;
+			buf[1] = (eax >> 8) & 0xFF;
+			buf[2] = (eax >> 16) & 0xFF;
+			buf[3] = (eax >> 24) & 0xFF;
+
+			buf[4] = ebx & 0xFF;
+			buf[5] = (ebx >> 8) & 0xFF;
+			buf[6] = (ebx >> 16) & 0xFF;
+			buf[7] = (ebx >> 24) & 0xFF;
+
+			buf[8] = ecx & 0xFF;
+			buf[9] = (ecx >> 8) & 0xFF;
+			buf[10] = (ecx >> 16) & 0xFF;
+			buf[11] = (ecx >> 24) & 0xFF;
+
+			buf[12] = edx & 0xFF;
+			buf[13] = (edx >> 8) & 0xFF;
+			buf[14] = (edx >> 16) & 0xFF;
+			buf[15] = (edx >> 24) & 0xFF;
 			break;
 		case CPUID_EXTENDED_L2_CACHE_FEATURES:
 			buf[0] = ecx & 0xFF; 		/* Line size.  */
diff --git a/ccan/cpuid/cpuid.h b/ccan/cpuid/cpuid.h
index 9bf4ff31..5de2ed15 100644
--- a/ccan/cpuid/cpuid.h
+++ b/ccan/cpuid/cpuid.h
@@ -38,6 +38,7 @@
  *
  * CPUID_CACHE_AND_TLBD_INFO
  * 	Cache and TLBD Information.
+ * 	For AMD: Use CPUID_EXTENDED_L2_CACHE_FEATURES
  *
  * CPUID_HIGHEST_EXTENDED_FUNCTION_SUPPORTED:
  * 	Highest extended function supported address.
@@ -51,6 +52,7 @@
  *
  * CPUID_L1_CACHE_AND_TLB_IDS:
  * 	L1 Cache and TLB Identifications.
+ *	AMD Only.
  *
  * CPUID_EXTENDED_L2_CACHE_FEATURES:
  * 	Extended L2 Cache features.
@@ -217,29 +219,32 @@ uint32_t cpuid_highest_ext_func_supported(void);
  * 	buf[2]: Family
  * 	buf[3]: Extended Model
  * 	buf[4]: Extended Family
- * 	buf[5] and buf[6]:
- * 		Feature flags
- * 	buf[7]: Brand Index
- * 	buf[8]: CL Flush Line Size
- * 	buf[9]: Logical Processors
- * 	buf[10]: Initial APICID
+ * 	buf[5]: Brand Index
+ * 	buf[6]: CL Flush Line Size
+ * 	buf[7]: Logical Processors
+ * 	buf[8]: Initial APICID
  *
  * For CPUID_L1_CACHE_AND_TLB_IDS:
- * 	buf[0]: (eax):
- * 		- 7..0 	Number of times to exec cpuid to get all descriptors.
- * 		- 15..8 Instruction TLB: 4K Pages, 4-way set associtive, 128 entries.
- * 		- 23..16 Data TLB: 4k Pages, 4-way set associtive, 128 entries.
- * 		- 24..31 Instruction TLB: 4K Pages, 4-way set associtive, 2 entries.
- * 	buf[1]: (ebx):
- * 		- 7..0 64-byte prefetching
- * 		- 8..31 Null descriptor
- * 	buf[2]: (ecx):
- * 		- 0..31 Null descriptor
- * 	buf[3]: (edx):
- * 		- 7..0 2nd-level cache, 2M, 8-way set associtive, 64-byte line size
- * 		- 15..8 1st-level instruction cache: 32K, 8-way set associtive, 64 byte line size
- * 		- 16..23 Data TLB: 4M Pages, 4-way set associtive, 8 entires.
- * 		- 24..31 1st-level data cache: 32K, 8-way set associtive, 64 byte line size
+ *	buf[0] to buf[3]: 2M+4M page TLB info
+ * 		0: Inst count
+ * 		1: Inst Assoc
+ * 		2: Data Count
+ * 		3: Data Assoc
+ * 	buf[4] to buf[7]: 4k page TLB info
+ * 		0: Inst count
+ * 		1: Inst Assoc
+ * 		2: Data Count
+ * 		3: Data Assoc
+ * 	buf[8] to buf[11]: L1 data cache information
+ *		0: Line Size
+ * 		1: LinesPerTag
+ * 		2: Associativity
+ * 		3: CacheSize
+ * 	buf[12] to buf[15]: L1 instruction cache info
+ * 		0: Line Size
+ * 		1: LinesPerTag
+ * 		2: Associativity
+ * 		3: CacheSize
  *
  * For CPUID_HIGHEST_EXTENDED_FUNCTION_SUPPORTED:
  * 	Returns the highest supported function in *buf (expects an integer ofc)
diff --git a/ccan/cpuid/test/run.c b/ccan/cpuid/test/run.c
index f7b52e41..0d2bebd6 100644
--- a/ccan/cpuid/test/run.c
+++ b/ccan/cpuid/test/run.c
@@ -18,12 +18,12 @@ int main(void)
 	cpuid(CPUID_PROC_BRAND_STRING, (uint32_t *)buf);
 	printf ("Processor Brand: %s\n", buf);
 
-	uint32_t procinfo[11];
+	uint32_t procinfo[9];
 	cpuid(CPUID_PROCINFO_AND_FEATUREBITS, procinfo);
 	printf("Stepping: %d Model: 0x%X Family: %d extended model: %d extended family: %d\n",
 		procinfo[0], procinfo[1], procinfo[2], procinfo[3], procinfo[4]);
 	printf("Brand Index: %d CL Flush Line Size: %d Logical Processors: %d Initial APICID: %d\n",
-		procinfo[7], procinfo[8], procinfo[9], procinfo[10]);
+		procinfo[5], procinfo[6], procinfo[7], procinfo[8]);
 
 	printf ("Highest extended function supported: %#010x\n", cpuid_highest_ext_func_supported());