1 #ifndef __ASM_PPC_PROCESSOR_H
2 #define __ASM_PPC_PROCESSOR_H
4 /* Bit encodings for Machine State Register (MSR) */
5 #define MSR_POW (1<<18) /* Enable Power Management */
6 #define MSR_TGPR (1<<17) /* TLB Update registers in use */
7 #define MSR_ILE (1<<16) /* Interrupt Little-Endian enable */
8 #define MSR_EE (1<<15) /* External Interrupt enable */
9 #define MSR_PR (1<<14) /* Supervisor/User privilege */
10 #define MSR_FP (1<<13) /* Floating Point enable */
11 #define MSR_ME (1<<12) /* Machine Check enable */
12 #define MSR_FE0 (1<<11) /* Floating Exception mode 0 */
13 #define MSR_SE (1<<10) /* Single Step */
14 #define MSR_BE (1<<9) /* Branch Trace */
15 #define MSR_FE1 (1<<8) /* Floating Exception mode 1 */
16 #define MSR_IP (1<<6) /* Exception prefix 0x000/0xFFF */
17 #define MSR_IR (1<<5) /* Instruction MMU enable */
18 #define MSR_DR (1<<4) /* Data MMU enable */
19 #define MSR_RI (1<<1) /* Recoverable Exception */
20 #define MSR_LE (1<<0) /* Little-Endian enable */
22 /* Bit encodings for Hardware Implementation Register (HID0)
23 on PowerPC 603, 604, etc. processors (not 601). */
24 #define HID0_EMCP (1<<31) /* Enable Machine Check pin */
25 #define HID0_EBA (1<<29) /* Enable Bus Address Parity */
26 #define HID0_EBD (1<<28) /* Enable Bus Data Parity */
27 #define HID0_SBCLK (1<<27)
28 #define HID0_EICE (1<<26)
29 #define HID0_ECLK (1<<25)
30 #define HID0_PAR (1<<24)
31 #define HID0_DOZE (1<<23)
32 #define HID0_NAP (1<<22)
33 #define HID0_SLEEP (1<<21)
34 #define HID0_DPM (1<<20)
35 #define HID0_ICE (1<<15) /* Instruction Cache Enable */
36 #define HID0_DCE (1<<14) /* Data Cache Enable */
37 #define HID0_ILOCK (1<<13) /* Instruction Cache Lock */
38 #define HID0_DLOCK (1<<12) /* Data Cache Lock */
39 #define HID0_ICFI (1<<11) /* Instruction Cache Flash Invalidate */
40 #define HID0_DCI (1<<10) /* Data Cache Invalidate */
41 #define HID0_SPD (1<<9) /* Speculative disable */
42 #define HID0_SIED (1<<7) /* Serial Instruction Execution [Disable] */
43 #define HID0_BHTE (1<<2) /* Branch History Table Enable */
44 #define HID0_BTCD (1<<1) /* Branch target cache disable */
47 #define FPSCR_FX (1<<31)
48 #define FPSCR_FEX (1<<30)
54 #define TBRU 269 /* Time base Upper/Lower (Reading) */
56 #define TBWU 284 /* Time base Upper/Lower (Writing) */
61 #define HID0 1008 /* Hardware Implementation */
62 #define PVR 287 /* Processor Version */
63 #define IBAT0U 528 /* Instruction BAT #0 Upper/Lower */
65 #define IBAT1U 530 /* Instruction BAT #1 Upper/Lower */
67 #define IBAT2U 532 /* Instruction BAT #2 Upper/Lower */
69 #define IBAT3U 534 /* Instruction BAT #3 Upper/Lower */
71 #define DBAT0U 536 /* Data BAT #0 Upper/Lower */
73 #define DBAT1U 538 /* Data BAT #1 Upper/Lower */
75 #define DBAT2U 540 /* Data BAT #2 Upper/Lower */
77 #define DBAT3U 542 /* Data BAT #3 Upper/Lower */
79 #define DMISS 976 /* TLB Lookup/Refresh registers */
86 #define SDR1 25 /* MMU hash base register */
87 #define DAR 19 /* Data Address Register */
88 #define SPR0 272 /* Supervisor Private Registers */
97 #define SRR0 26 /* Saved Registers (exception) */
99 #define IABR 1010 /* Instruction Address Breakpoint */
100 #define DEC 22 /* Decrementer */
101 #define EAR 282 /* External Address Register */
102 #define L2CR 1017 /* PPC 750 L2 control register */
107 #define THRM1_TIN 0x1
108 #define THRM1_TIV 0x2
109 #define THRM1_THRES (0x7f<<2)
110 #define THRM1_TID (1<<29)
111 #define THRM1_TIE (1<<30)
112 #define THRM1_V (1<<31)
113 #define THRM3_E (1<<31)
115 /* Segment Registers */
134 static __inline__ unsigned long mfmsr(void)
137 __asm__ __volatile__("mfmsr %0" : "=r" (msr));
142 #endif /* __ASM_PPC_PROCESSOR_H */